Freescale Semiconductor MCF54455 Reference Manual page 100

Table 3-18. EMAC Instruction Execution Times (continued)
Opcode
MOVE.L MACSR, <ea>x
MOVE.L Rmask, <ea>x
MOVE.L Raccext01,<ea.x
MOVE.L Raccext23,<ea>x
MSAC.L Ry, Rx, Raccx
MSAC.W Ry, Rx, Raccx
MSAC.L Ry, Rx, <ea>, Rw, Raccx
MSAC.W Ry, Rx, <ea>, Rw, Raccx
MULS.L <ea>y, Dx
MULS.W <ea>y, Dx
MULU.L <ea>y, Dx
MULU.W <ea>y, Dx
1
Effective address of (d16,PC) not supported
2
Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional
rounding is performed (MACSR[7:4] equals 1---, -11-, --11)
The execution times for moving the contents of the Racc, Raccext[01,23],
MACSR, or Rmask into a destination location <ea>x shown in this table
represent the best-case scenario when the store instruction is executed and
there are no load or M{S}AC instructions in the EMAC execution pipeline.
In general, these store operations require only a single cycle for execution,
but if preceded immediately by a load, MAC, or MSAC instruction, the
depth of the EMAC pipeline is exposed and the execution time is four
cycles.
3.3.5.7 Branch Instruction Execution Times
Opcode <EA>
Rn
BRA —
BSR —
Freescale Semiconductor
<EA>
Rn (An)
1(0/0) —
1(0/0) —
1(0/0) —
1(0/0) —
1(0/0) —
1(0/0) —
— 1(1/0)
— 1(1/0)
4(0/0) 4(1/0)
4(0/0) 4(1/0)
4(0/0) 4(1/0)
4(0/0) 4(1/0)
NOTE
Table 3-19. General Branch Instruction Execution Times
(An) (An)+
— —
— —
Effective Address
(An)+ -(An) (d16,An)
— — —
— — —
— — —
— — —
— — —
— — —
1
1(1/0) 1(1/0) 1(1/0)
1
1(1/0) 1(1/0) 1(1/0)
4(1/0) 4(1/0) 4(1/0)
4(1/0) 4(1/0) 4(1/0)
4(1/0) 4(1/0) 4(1/0)
4(1/0) 4(1/0) 4(1/0)
Effective Address
(d16,An) (d8,An,Xi*SF)
-(An)
(d16,PC) (d8,PC,Xi*SF)
1
— 1(0/1) —
2
— 1(0/1) —
ColdFire Core
(d8,An,
xxx.wl #xxx
Xn*SF)
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
5(1/0) 4(1/0) 4(0/0)
— — —
5(1/0) 4(1/0) 4(0/0)
xxx.wl #xxx
— —
— —
3-34