Freescale Semiconductor MCF54455 Reference Manual page 550

22.4.1.5.2 I/O Space Addressing
For PCI I/O accesses, all 32 address signals provide an address with granularity of a single byte. After a
target has claimed an I/O access, it must determine if it can complete the entire access as indicated by the
byte enable signals. If all selected bytes are not in the address range of the target, the entire access cannot
complete. In this case, target does not transfer any data and terminates the transaction with a target-abort.
Access Size
22.4.1.5.3 Configuration Space Addressing and Transactions
PCI supports two types of configuration accesses. Their primary difference is the format of the address on
the PCI_AD[31:0] signals during the address phase. The two low-order bits of the address indicate the
format used for the configuration address phase: type 0 (AD[1:0] equals 0b00) or type 1 (AD[1:0] equals
0b01). Both address formats identify a specific device and a specific configuration register for that device:
• Type 0 configuration accesses select a device on the local PCI bus. They do not propagate beyond
the local PCI bus and are claimed by a local device or terminated with a master-abort.
• Type 1 configuration accesses target a device on a subordinate bus through a PCI-to-PCI bridge,
see Figure 22-39. Type 1 accesses are ignored by all targets except PCI-to-PCI bridges that pass
the configuration request to another PCI bus.
When the controller initiates a configuration access on the PCI bus, it places the configuration address
information on the AD bus and the configuration command on the PCI_CBE[3:0] bus. Setting AD[1:0] to
0b00 during the address phase indicates a Type 0 configuration transaction. The bit pattern tells the
community of devices on the PCI bus the bridge that owns the PCI bus has already performed the bus
number comparison and verified the request targets a device on its bus.
of the AD bus during the address phase of the Type 0 configuration access.
Freescale Semiconductor
Table 22-27. PCI I/O Space Byte Decoding
PCI_AD[1:0]
8-bit 00
01
10
11
16-bit 00
01
10
24-bit 00
01
32-bit 00
PCI_CBE[3:0] Data
xxx0 AD[7:0]
xx01 AD[15:8]
x011 AD[23:16]
0111 AD[31:24]
xxx0 AD[15:0]
xx01 AD[23:8]
x011 AD[31:16]
xxx0 AD[23:0]
xx01 AD[31:8]
xxx0 AD[31:0]
Figure 22-37
PCI Bus Controller
shows the contents
22-33