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Field
7
Reserved, must be cleared.
6
Clear all enable requests.
CAER
0 Clear only those EDMA_ERQ bits specified in the CERQ field.
1 Clear all bits in EDMA_ERQ.
5–4
Reserved, must be cleared.
3–0
Clear enable request. Clears the corresponding bit in EDMA_ERQ.
CERQ
19.4.7
eDMA Set Enable Error Interrupt Register (EDMA_SEEI)
The EDMA_SEEI provides a simple memory-mapped mechanism to set a given bit in the EDMA_EEI to
enable the error interrupt for a given channel. The data value on a register write causes the corresponding
bit in the EDMA_EEI to be set. Setting the SAEE bit provides a global set function, forcing the entire
EDMA_EEI contents to be set. Reads of this register return all zeroes.
Address: 0xFC04_401A (EDMA_SEEI)
7
R
0
W
SAEE
Reset
0
Figure 19-9. eDMA Set Enable Error Interrupt Register (EDMA_SEEI)
Field
7
Reserved, must be cleared.
6
Sets all enable error interrupts.
SAEE
0 Set only those EDMA_EEI bits specified in the SEEI field.
1 Sets all bits in EDMA_EEI.
5–4
Reserved, must be cleared.
3–0
Set enable error interrupt. Sets the corresponding bit in EDMA_EEI.
SEEI
19.4.8
eDMA Clear Enable Error Interrupt Register (EDMA_CEEI)
The EDMA_CEEI provides a simple memory-mapped mechanism to clear a given bit in the EDMA_EEI
to disable the error interrupt for a given channel. The data value on a register write causes the
corresponding bit in the EDMA_EEI to be cleared. Setting the CAEE bit provides a global clear function,
forcing the EDMA_EEI contents to be cleared, disabling all DMA request inputs. Reads of this register
return all zeroes.
Freescale Semiconductor
Table 19-9. EDMA_CERQ Field Descriptions
6
5
0
0
0
0
Table 19-10. EDMA_SEEI Field Descriptions
Enhanced Direct Memory Access (eDMA)
Description
4
3
0
0
0
0
Description
Access: User write-only
2
1
0
0
SEEI
0
0
0
0
0
19-11
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