Freescale Semiconductor MCF54455 Reference Manual page 914

External synchronization is required to achieve meaningful results because
there is no internal synchronization between TCLK and the system clock.
35.4.3.4 EXTEST Instruction
The external test (EXTEST) instruction selects the boundary scan register. It forces all output pins and
bidirectional pins configured as outputs to the values preloaded with the SAMPLE/PRELOAD instruction
and held in the boundary scan update registers. EXTEST can also configure the direction of bidirectional
pins and establish high-impedance states on some pins. EXTEST asserts internal reset for the MCU system
logic to force a predictable internal state while performing external boundary scan operations.
35.4.3.5 ENABLE_TEST_CTRL Instruction
The ENABLE_TEST_CTRL instruction selects a 1-bit shift register (TEST_CTRL) for connection as a
shift path between the TDI and TDO pin. When the user transitions the TAP controller to the UPDATE_DR
state, the register transfers its value to a parallel hold register.
35.4.3.6 HIGHZ Instruction
The HIGHZ instruction eliminates the need to backdrive the output pins during circuit-board testing.
HIGHZ turns off all output drivers, including the 2-state drivers, and selects the bypass register. HIGHZ
also asserts internal reset for the MCU system logic to force a predictable internal state.
35.4.3.7 CLAMP Instruction
The CLAMP instruction selects the 1-bit bypass register and asserts internal reset while simultaneously
forcing all output pins and bidirectional pins configured as outputs to the fixed values that are preloaded
and held in the boundary scan update register. CLAMP enhances test efficiency by reducing the overall
shift path to a single bit (the bypass register) while conducting an EXTEST type of instruction through the
boundary scan register.
35.4.3.8 BYPASS Instruction
The BYPASS instruction selects the bypass register, creating a single-bit shift register path from the TDI
pin to the TDO pin. BYPASS enhances test efficiency by reducing the overall shift path when a device
other than the ColdFire processor is the device under test on a board design with multiple chips on the
overall boundary scan chain. The shift register lsb is forced to logic 0 on the rising edge of TCLK after
entry into the capture-DR state. Therefore, the first bit shifted out after selecting the bypass register is
always logic 0. This differentiates parts that support an IDCODE register from parts that support only the
bypass register.
Freescale Semiconductor
NOTE
IEEE 1149.1 Test Access Port (JTAG)
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