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Appendix A
Revision History
This appendix lists major changes between versions of the MCF54455RM document.
A.1
Changes Between Rev. 2 and Rev. 3
Chapter
Added PCI as feature on 256-pin devices in family comparison table. On these devices the PCI_AD bus is limited
Overview
to 24-bits.
Corrected minimum core frequency in Features list from 18.75 MHz to 75 MHz
SRAM
Added RAMBAR[D/I] bit.
Corrected FB_AD[7:5] - Flexbus, PCI, Port Size Mode (256-pin Devices) entry in Parallel Configuration During Reset
table to match table in CCR Field Descriptions 256-pin's FBCONFIG field.
CCM
In Serial Configuration During Reset table, changed Pins Affected column for PCI and Flexbus A/D Pin Mode to
"PCI_AD[31:0] (360-pin) PCI_AD[23:0] (256-pin)"
SBF
The default clock divisor is 67 when first booting from SPI memory, prior to loading the BLDIV value.
Changed CWSR section note from "If the CWT is enabled, then any write" to "If the CWT is enabled and has not
timed out, any write..."
Changed core watchdog timer functional description section note from "If the CWT is enabled, then any write" to "If
the CWT is enabled and has not timed out, any write..."
Added "The SCMISR[CFEI] bit flags fault errors independent of the CFIER[ECFEI] setting. Therefore, if CFEI is set
SCM
prior to setting ECFEI, an interrupt is requested immediately after ECFEI is set." to end of SCMISR section.
Added "Note: This bit reports core faults regardless of the setting of CFIER[ECFEI]. Therefore, if the error interrupt
is disabled and a core fault occurs, this bit is set. Then, if the error interrupt is subsequently enabled, an interrupt
is immediately requested. To prevent an undesired interrupt, clear the captured error by writing one to CFEI
before enabling the interrupt." to end of SCMISR[CFEI] bit description.
Reworded Initialization/Application Info section example steps.
Interrupt
Removed ICONFIG1 register and added note to this section. Similar to the SLMASK and CLMASK registers, there
Controller
is only one version of this register located in the INTC0 space.
Edge Port Added bit 0 for each EPORT register, although this bit may not be used on this particular device.
DMA
Added external signal timing section.
Freescale Semiconductor
Table A-1. Rev. 2 to Rev. 3 Changes
Description
A-1
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