Features - Freescale Semiconductor MCF54455 Reference Manual

Cryptographic Acceleration Unit (CAU)
• SHA-1
This selection of algorithms provides excellent support for network security standards (SSL, IPsec).
Additionally, using the CAU efficiently permits the implementation of any higher level functions or modes
of operation (HMAC, CBC, etc.) based on the supported algorithm.
The CAU is an instruction-level ColdFire coprocessor. The cryptographic algorithms are implemented
partially in software with only functions critical to increasing performance implemented in hardware. The
ColdFire coprocessor allows for efficient, fine-grained partitioning of functions between hardware and
software.
• Implement the innermost round functions by using the coprocessor instructions
• Implement higher-level functions in software by using the standard ColdFire instructions
This partitioning of functions is key to minimizing size of the CAU while maintaining a high level of
throughput. Using software for some functions also simplifies the CAU design. The CAU implements a
set of 22 coprocessor commands that operate on a register file of eight 32-bit registers. It is tightly coupled
to the ColdFire core and there is no local memory or external interface.
24.1.3

Features

The CAU includes these distinctive features:
• Supports DES, 3DES, AES, MD5, SHA-1 algorithms
• Simple, flexible programming model
24.2 Memory Map/Register Definition
The CAU only supports longword operations and register accesses. All registers support read, write, and
ALU operations. However, only bits 1–0 of the CASR are writeable. Bits 31–2 of the CASR must be
written as 0 for compatibility with future versions of the CAU.
Code
0 CAU status register (CASR)
1 CAU accumulator (CAA)
2 General purpose register 0 (CA0)
3 General purpose register 1 (CA1)
4 General purpose register 2 (CA2)
5 General purpose register 3 (CA3)
6 General purpose register 4 (CA4)
7 General purpose register 5 (CA5)
24-3
Table 24-1. CAU Memory Map
Register
—
—
C
D
L
R
—
—
Access Reset Value
— — — R/W 0x1000_0000
— T a R 0x0000_0000
W0 A — R 0x0000_0000
W1 B b R 0x0000_0000
W2 C c R 0x0000_0000
W3 D d R 0x0000_0000
— E — R 0x0000_0000
— W — R 0x0000_0000
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