Sdram Ddr Component Connections; Ddr Sdram Layout Considerations - Freescale Semiconductor MCF54455 Reference Manual

SDRAM Controller (SDRAMC)
21.3.2

SDRAM DDR Component Connections

Figure 21-2 shows a block diagram using 16-bit wide DDR SDRAM (such as Micron MT46V8M16) and
flash (such as Spansion AM29DBB160G).
SDRAM Controller
SD_CLK
SD_CLK
SD_CKE
SD_CS0
SD_RAS
SD_CAS
SD_WE
SD_A10
SD_DQS[3:2]
SD_DQM[3:2]
SD_BA[1:0]
SD_A[13:0]
SD_D[31:16]
SD_VREF
21.3.3

DDR SDRAM Layout Considerations

Due to the critical timing for DDR SDRAM, a number of considerations should be taken into account
during PCB layout:
• Minimize overall trace lengths.
• Each DQS, DM, and DQ group must have identical loading and similar routing to maintain timing
integrity.
• Control and clock signals are routed point-to-point.
• Trace length for clock, address, and command signals should match.
• Route DDR signals on layers adjacent to the ground plane.
• Use a VREF plane under the SDRAM.
• VREF is decoupled from SDVDD and VSS.
• To avoid crosstalk, address and command signals must remain separate from data and data strobes.
• Use different resistor packs for command/address and data/data strobes.
21-8
1.25 V
Figure 21-2. Example 2.5V, 16-bit DDR SDRAM System
2.5V DDR SDRAM
CLK
CLK
CKE
CS
RAS
CAS
WE
A10/AP
DQS[1:0]
DQM[3:2]
BA[1:0]
A[13:11,9:0]
D[15:0]
1.25V
VREF
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