Freescale Semiconductor MC9S08PT60 Manuals

Manuals and User Guides for Freescale Semiconductor MC9S08PT60. We have 1 Freescale Semiconductor MC9S08PT60 manual available for free PDF download: Reference Manual

Freescale Semiconductor MC9S08PT60 Reference Manual (679 pages)

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 7 MB

Table of Contents
3
Chapter 1 Device Overview

35
- Introduction
  35
- MCU Block Diagram
  36
- System Clock Distribution
  38
Chapter 2 Pins and Connections

41
- Device Pin Assignment
  41
- Pin Functions
  45
Chapter 3 Power Management

55
- Introduction
  55
- Features
  55
  - Run Mode
    55
  - Wait Mode
    56
  - Stop3 Mode
    56
  - Active BDM Enabled in Stop3 Mode
    56
  - LVD Enabled in Stop Mode
    57
  - Power Modes Behaviors
    57
- Low Voltage Detect (LVD) System
  58
- Bandgap Reference
  60
- Power Management Control Bits and Registers
  60
  - System Power Management Status and Control 1 Register (PMC_SPMSC1)
    60
  - System Power Management Status and Control 2 Register (PMC_SPMSC2)
    62
Chapter 4 Memory Map

63
Chapter 5 Interrupt

121
- Interrupts
  121
- Irq
  129
  - Features
    130
    
    Edge and Level Sensitivity
    131
    
    Pin Configuration Options
    131
- Interrupt Pin Request Register
  131
  - Interrupt Pin Request Status and Control Register (IRQ_SC)
    132
- Interrupt Priority Control Register
  133
Chapter 6 System Control

137
Chapter 7 Parallel Input/Output

157
Chapter 8 Clock Management

201
- Clock Module
  201
- Internal Clock Source (ICS)
  203
  - Function Description
    203
    
    Bus Frequency Divider
    204
    
    Internal Reference Clock (ICSIRCLK)
    204
    
    Low Power Bit Usage
    204
    
    Fixed Frequency Clock (ICSFFCLK)
    205
    
    BDC Clock
    206
  - Modes of Operation
    206
    
    FLL Engaged Internal (FEI)
    207
    
    FLL Bypassed Internal (FBI)
    208
    
    FLL Bypassed Internal Low Power (FBILP)
    208
    
    FLL Engaged External (FEE)
    208
    
    FLL Bypassed External (FBE)
    209
    
    FLL Bypassed External Low Power (FBELP)
    209
    
    Stop (STOP)
    210
  - FLL Lock and Clock Monitor
    211
    
    External Reference Clock Monitor
    211
    
    FLL Clock Lock
    211
- Initialization / Application Information
  211
  - Initializing FEI Mode
    212
  - Initializing FBI Mode
    212
  - Initializing FEE Mode
    212
  - Initializing FBE Mode
    213
  - External Oscillator (OSC)
    213
    
    Bypass Mode
    214
    
    Low-Power Configuration
    214
    
    High-Gain Configuration
    215
    
    Initializing External Oscillator for Peripherals
    215
- Khz Low-Power Oscillator (LPO)
  216
- Peripheral Clock Gating
  216
- ICS Control Registers
  216
- System Clock Gating Control Registers
  222
Chapter 9 Chip Configurations

229
- Introduction
  229
- Core Modules
  229
  - Central Processor Unit (CPU)
    229
  - Debug Module (DBG)
    229
- System Modules
  230
  - Watchdog (WDOG)
    230
- Clock Module
  230
- Memory
  232
  - Random-Access-Memory (RAM)
    232
  - Non-Volatile Memory (NVM)
    232
- Power Modules
  232
- Security
  233
  - Cyclic Redundancy Check (CRC)
    233
- Timers
  235
  - Flextimer Module (FTM)
    235
    
    FTM0 Interconnection
    237
    
    FTM1 Interconnection
    237
    
    FTM2 Interconnection
    237
  - 8-Bit Modulo Timer (MTIM)
    237
    
    MTIM0 as ADC Hardware Trigger
    239
  - Real-Time Counter (RTC)
    239
- Communication Interfaces
  241
- Analog
  250
  - Analog-To-Digital Converter (ADC)
    250
    
    ADC Channel Assignments
    251
    
    Alternate Clock
    253
    
    Hardware Trigger
    253
    
    Temperature Sensor
    253
  - Analog Comparator (ACMP)
    254
    
    ACMP Configuration Information
    256
    
    ACMP for SCI0 RXD Filter
    256
    
    ACMP in Stop3 Mode
    256
    
    ACMP to FTM Configuration Information
    256
- Human-Machine Interfaces HMI
  257
  - Keyboard Interrupts (KBI)
    257
  - Touch Sense Input (TSI)
    259
    
    TSI Channel Assignments
    260
    
    Hardware Trigger
    261
Chapter 10 Central Processor Unit

263
- Introduction
  263
  - Features
    263
- Programmer's Model and CPU Registers
  264
  - Accumulator (A)
    264
  - Index Register (H:X)
    265
  - Stack Pointer (SP)
    265
  - Program Counter (PC)
    266
  - Condition Code Register (CCR)
    266
- Addressing Modes
  267
  - Inherent Addressing Mode (INH)
    268
  - Relative Addressing Mode (REL)
    268
  - Immediate Addressing Mode (IMM)
    268
  - Direct Addressing Mode (DIR)
    269
  - Extended Addressing Mode (EXT)
    269
  - Indexed Addressing Mode
    270
    
    Indexed, 8-Bit Offset (IX1)
    270
    
    Indexed, no Offset (IX)
    270
    
    Indexed, no Offset with Post Increment (IX+)
    270
    
    Indexed, 16-Bit Offset (IX2)
    271
    
    Indexed, 8-Bit Offset with Post Increment (IX1+)
    271
    
    SP-Relative, 8-Bit Offset (SP1)
    271
    
    SP-Relative, 16-Bit Offset (SP2)
    272
  - Memory to Memory Addressing Mode
    272
    
    Direct to Direct
    272
    
    Immediate to Direct
    272
    
    Direct to Indexed, Post-Increment
    273
    
    Indexed to Direct, Post Increment
    273
- Operation Modes
  273
  - Stop Mode
    273
  - Wait Mode
    274
  - Background Mode
    274
  - Security Mode
    275
- HCS08 V6 Opcodes
  277
- Special Operations
  277
  - Reset Sequence
    277
  - Interrupt Sequence
    277
- Instruction Set Summary
  278
Chapter 11 Keyboard Interrupts (KBI)

291
- Introduction
  291
  - Features
    291
  - Modes of Operation
    291
    
    KBI in Wait Mode
    291
    
    KBI in Active Background Mode
    292
    
    KBI in Stop Modes
    292
  - Block Diagram
    292
- External Signals Description
  293
- Register Definition
  293
- Memory Map and Registers
  293
- Functional Description
  295
  - Edge-Only Sensitivity
    296
  - Edge and Level Sensitivity
    296
  - KBI Pullup Resistor
    296
  - KBI Initialization
    297
Chapter 12 Flextimer Module (FTM)

299
- Introduction
  299
  - Flextimer Philosophy
    299
  - Features
    300
  - Modes of Operation
    301
  - Block Diagram
    302
- Signal Description
  304
  - EXTCLK - FTM External Clock
    304
  - Chn - FTM Channel (N) I/O Pin
    304
  - Faultj - FTM Fault Input
    304
- Memory Map and Register Definition
  305
  - Module Memory Map
    305
  - Register Descriptions
    305
  - Status and Control (Ftmx_Sc)
    309
  - Counter High (Ftmx_Cnth)
    310
  - Counter Low (Ftmx_Cntl)
    311
  - Modulo High (Ftmx_Modh)
    311
  - Modulo Low (Ftmx_Modl)
    312
  - Channel Status and Control (Ftmx_Cnsc)
    312
  - Channel Value High (Ftmx_Cnvh)
    315
  - Channel Value Low (Ftmx_Cnvl)
    316
  - Counter Initial Value High (Ftmx_Cntinh)
    316
  - Counter Initial Value Low (Ftmx_Cntinl)
    317
  - Capture and Compare Status (Ftmx_Status)
    317
  - Features Mode Selection (Ftmx_Mode)
    319
  - Synchronization (Ftmx_Sync)
    320
  - Initial State for Channel Output (Ftmx_Outinit)
    322
  - Output Mask (Ftmx_Outmask)
    324
  - Function for Linked Channels (Ftmx_Combinen)
    325
  - Deadtime Insertion Control (Ftmx_Deadtime)
    327
  - External Trigger (Ftmx_Exttrig)
    328
  - Channels Polarity (Ftmx_Pol)
    329
  - Fault Mode Status (Ftmx_Fms)
    331
  - Input Capture Filter Control (Ftmx_Filtern)
    332
  - Fault Input Filter Control (Ftmx_Fltfilter)
    333
  - Fault Input Control (Ftmx_Fltctrl)
    334
- Functional Description
  335
  - Clock Source
    336
    
    Counter Clock Source
    336
  - Prescaler
    337
  - Counter
    337
    
    Up Counting
    337
    
    Up-Down Counting
    340
  - Free Running Counter
    341
  - Counter Reset
    342
- Input Capture Mode
  342
  - Filter for Input Capture Mode
    343
- Output Compare Mode
  344
- Edge-Aligned PWM (EPWM) Mode
  346
- Center-Aligned PWM (CPWM) Mode
  348
- Combine Mode
  350
  - Asymmetrical PWM
    357
- Complementary Mode
  357
- Update of the Registers with Write Buffers
  358
  - CNTINH:L Registers
    358
  - MODH:L Registers
    358
  - Cnvh:l Registers
    359
- PWM Synchronization
  360
  - Hardware Trigger
    360
  - Software Trigger
    361
  - Boundary Cycle
    362
  - MODH:L Registers Synchronization
    363
  - Cnvh:l Registers Synchronization
    365
  - OUTMASK Register Synchronization
    366
  - FTM Counter Synchronization
    367
  - Summary of PWM Synchronization
    369
- Deadtime Insertion
  371
  - Deadtime Insertion Corner Cases
    372
- Output Mask
  373
- Fault Control
  374
  - Automatic Fault Clearing
    376
  - Manual Fault Clearing
    377
  - Polarity Control
    378
  - Initialization
    378
  - Features Priority
    379
  - Channel Trigger Output
    379
  - Initialization Trigger
    380
  - Capture Test Mode
    382
  - Dual Edge Capture Mode
    383
    
    Continuous Capture Mode
    385
    
    One-Shot Capture Mode
    385
    
    Pulse Width Measurement
    386
    
    Period Measurement
    388
    
    Read Coherency Mechanism
    390
  - TPM Emulation
    392
    
    Free Running Counter
    392
    
    MODH:L and Cnvh:l Synchronization
    392
    
    Write to Cnsc
    392
    
    Write to SC
    392
  - BDM Mode
    393
- Reset Overview
  393
- FTM Interrupts
  395
  - Timer Overflow Interrupt
    395
  - Channel (N) Interrupt
    395
  - Fault Interrupt
    395
Chapter 13 8-Bit Modulo Timer (MTIM)

397
- Introduction
  397
- Features
  397
- Modes of Operation
  397
  - MTIM in Wait Mode
    398
  - MTIM in Stop Mode
    398
  - MTIM in Active Background Mode
    398
- Block Diagram
  398
- External Signal Description
  399
- Register Definition
  399
- Functional Description
  402
  - MTIM Operation Example
    404
Chapter 14 Real-Time Counter (RTC)

405
- Introduction
  405
- Features
  405
  - Modes of Operation
    405
    
    Stop Modes
    406
    
    Wait Mode
    406
  - Block Diagram
    406
- External Signal Description
  406
- Register Definition
  407
- Functional Description
  411
  - RTC Operation Example
    412
- Initialization/Application Information
  414
Chapter 15 Serial Communications Interface (SCI)

415
- Introduction
  415
  - Features
    415
  - Modes of Operation
    415
  - Block Diagram
    416
- SCI Signal Descriptions
  418
  - Detailed Signal Descriptions
    418
- Register Definition
  418
- Functional Description
  429
  - Baud Rate Generation
    429
  - Transmitter Functional Description
    430
    
    Send Break and Queued Idle
    430
  - Receiver Functional Description
    432
    
    Data Sampling Technique
    432
    
    Receiver Wake-Up Operation
    433
  - Interrupts and Status Flags
    434
  - Baud Rate Tolerance
    435
    
    Slow Data Tolerance
    436
    
    Fast Data Tolerance
    437
  - Additional SCI Functions
    438
    
    8- and 9-Bit Data Modes
    438
    
    Stop Mode Operation
    438
    
    Loop Mode
    439
    
    Single-Wire Operation
    439
Chapter 16 8-Bit Serial Peripheral Interface (8-Bit SPI)

441
- Introduction
  441
  - Features
    441
  - Modes of Operation
    442
  - Block Diagrams
    442
    
    SPI Module Block Diagram
    443
    
    SPI System Block Diagram
    443
- External Signal Description
  444
  - SPSCK - SPI Serial Clock
    445
  - MOSI - Master Data Out, Slave Data in
    445
  - MISO - Master Data In, Slave Data out
    445
  - SS - Slave Select
    445
- Register Definition
  446
  - SPI Control Register 1 (Spix_C1)
    446
  - SPI Control Register 2 (Spix_C2)
    448
  - SPI Baud Rate Register (Spix_Br)
    449
  - SPI Status Register (Spix_S)
    450
  - SPI Data Register (Spix_D)
    451
  - SPI Match Register (Spix_M)
    452
- Functional Description
  452
  - General
    452
  - Master Mode
    453
  - Slave Mode
    454
- SPI Clock Formats
  456
- SPI Baud Rate Generation
  459
  - Bidirectional Mode (MOMI or SISO)
    460
- Error Conditions
  461
- Low Power Mode Options
  462
  - SPI in Stop Mode
    463
  - Interrupts
    464
  - Sptef
    465
  - Pseudo-Code Example
    466
Chapter 25 Introduction

469
- Modes of Operation
  470
- Block Diagrams
  471
- SPI Module Block Diagram
  472
  - External Signal Description
    473
  - SPSCK — SPI Serial Clock
    474
Chapter 18 Memory Map/Register Definition

475
- SPI Control Register 2 (Spix_C2)
  477
- SPI Baud Rate Register (Spix_Br)
  478
- SPI Status Register (Spix_S)
  479
- SPI Data Register High (Spix_Dh)
  482
- SPI Data Register Low (Spix_Dl)
  483
- SPI Match Register High (Spix_Mh)
  484
- SPI Control Register 3 (Spix_C3)
  485
- SPI Clear Interrupt Register (Spix_Ci)
  486
  - General
    488
  - Slave Mode
    489
- SPI FIFO Mode
  491
- Data Transmission Length
  492
  - SPI Clock Formats
    493
  - SPI Baud Rate Generation
    496
  - Bidirectional Mode (MOMI or SISO)
    497
  - Error Conditions
    498
  - Low-Power Mode Options
    499
    
    SPI in Stop Mode
    500
    
    Interrupts
    501
    
    Sptef
    502
    
    Initialization/Application Information
    503
    
    Introduction
    507
Chapter 21

508
- Modes of Operation
  508
  - Signal Descriptions
    509
  - Memory Map/Register Definition
    510
- I2C Frequency Divider Register (I2C_F)
  511
- I2C Control Register 1 (I2C_C1)
  512
- I2C Status Register (I2C_S)
  513
- I2C Data I/O Register (I2C_D)
  515
- I2C Control Register 2 (I2C_C2)
  516
- I2C Range Address Register (I2C_RA)
  517
- I2C Address Register 2 (I2C_A2)
  519
- I2C SCL Low Timeout Register Low (I2C_SLTL)
  520
  - START Signal
    521
  - Data Transfers
    522
  - Repeated START Signal
    523
  - Handshaking
    524
- Bit Address
  526
- Address Matching
  527
- System Management Bus Specification
  528
  - FAST ACK and NACK
    530
  - Interrupts
    531
  - Exit from Low-Power/Stop Modes
    532
- Programmable Input Glitch Filter
  533
  - Initialization/Application Information
    534
  - Introduction
    537
  - Block Diagram
    538
Chapter 19

540
- Analog Channel Inputs (Adx)
  540
- Status and Control Register 2 (ADC_SC2)
  542
- Status and Control Register 3 (ADC_SC3)
  543
- Status and Control Register 4 (ADC_SC4)
  544
- Conversion Result High Register (ADC_RH)
  545
- Conversion Result Low Register (ADC_RL)
  546
- Compare Value High Register (ADC_CVH)
  547
- Pin Control 1 Register (ADC_APCTL1)
  548
- Pin Control 2 Register (ADC_APCTL2)
  549
  - Functional Description
    550
  - Clock Select and Divide Control
    551
  - Hardware Trigger
    552
    
    Completing Conversions
    553
    
    Power Control
    554
  - Automatic Compare Function
    556
  - MCU Wait Mode Operation
    560
- Initialization Information
  561
  - Pseudo-Code Example
    562
  - Pseudo-Code Example
    563
- Application Information
  564
  - Analog Reference Pins
    565
  - Sources of Error
    566
    
    Code Width and Quantization Error
    568
    
    Code Jitter, Non-Monotonicity, and Missing Codes
    569
    
    Introduction
    571
    
    Modes of Operation
    572
    
    External Signal Description
    573
Chapter 20

574
- ACMP Control and Status Register (ACMP_CS)
  574
- ACMP Control Register 0 (ACMP_C0)
  575
- ACMP Control Register 2 (ACMP_C2)
  576
- Setup and Operation of ACMP
  577
- Resets
  578
  - Introduction
    579
  - Modes of Operation
    580
  - External Signal Description
    581
- TSI Control and Status Register 0 (TSI_CS0)
  582
- TSI Control and Status Register 1 (TSI_CS1)
  583
- TSI Control and Status Register 2 (TSI_CS2)
  585
- TSI Control and Status Register 3 (TSI_CS3)
  586
- TSI Pin Enable Register 0 (TSI_PEN0)
  587
- TSI Pin Enable Register 1 (TSI_PEN1)
  588
- TSI Counter Register: High (TSI_CNTH)
  589
- TSI Measurement Result
  593
- Software and Hardware Trigger
  594
- Current Source
  595
- End of Scan
  596
  - Introduction
    603
  - Modes of Operation
    604
Chapter 22

605
- CRC Data 0 Register (CRC_D0)
  605
- CRC Data 2 Register (CRC_D2)
  606
- CRC Data 3 Register (CRC_D3)
  607
- CRC Polynomial 1 Register (CRC_P1)
  608
- CRC Polynomial 3 Register (CRC_P3)
  609
- Functional Description
  610
- Bit Reverse
  611
  - Introduction
    613
  - Block Diagram
    614
  - Memory Map and Register Definition
    615
- Watchdog Control and Status Register 2 (WDOG_CS2)
  617
- Watchdog Counter Register: High (WDOG_CNTH)
  618
- Watchdog Timeout Value Register: High (WDOG_TOVALH)
  619
- Watchdog Window Register: High (WDOG_WINH)
  620
  - Functional Description
    621
  - Window Mode
    622
  - Example Code: Refreshing the Watchdog
    623
  - Reconfiguring the Watchdog
    624
- Using Interrupts to Delay Resets
  626
- Fast Testing of the Watchdog
  627
  - Entering User Mode
    628
  - Introduction
    629
- Background Debug Controller (BDC)
  630
  - BKGD Pin Description
    631
  - Communication Details
    632
  - BDC Commands
    634
  - BDC Hardware Breakpoint
    637
  - Comparators a and B
    638
  - Bus Capture Information and FIFO Operation
    639
  - Change-Of-Flow Information
    640
  - Trigger Modes
    641
  - Hardware Breakpoints
    642
- Memory Map and Register Description
  643
  - BDC Breakpoint Match Register: High (BDC_BKPTH)
    645
  - BDC Breakpoint Register: Low (BDC_BKPTL)
    646
    
    Introduction
    649
    
    Modes of Operation
    650
    
    Signal Description
    651
  - Debug Comparator a High Register (DBG_CAH)
    652
  - Debug Comparator a Low Register (DBG_CAL)
    653
  - Debug Comparator B High Register (DBG_CBH)
    654
- Debug Comparator C High Register (DBG_CCH)
  655
- Debug Comparator C Low Register (DBG_CCL)
  656
- Debug FIFO Low Register (DBG_FL)
  657
- Debug Comparator a Extension Register (DBG_CAX)
  658
- Debug Comparator B Extension Register (DBG_CBX)
  659
- Debug Comparator C Extension Register (DBG_CCX)
  660
- Debug FIFO Extended Information Register (DBG_FX)
  661
- Debug Trigger Register (DBG_T)
  662
- Debug Status Register (DBG_S)
  664
- Debug Count Status Register (DBG_CNT)
  665
- Functional Description
  666
- Breakpoints
  667
- Trigger Selection
  668
  - Begin- and End-Trigger
    669
  - Trigger Modes
    670
- Fifo
  672
  - Storing Data in FIFO
    673
  - Reading Data from FIFO
    674

Freescale Semiconductor Categories

Motherboard Computer Hardware Microcontrollers Control Unit Controller

More Freescale Semiconductor Manuals

Freescale Semiconductor MC9S08PT60 Manuals

Freescale Semiconductor MC9S08PT60 Reference Manual (679 pages)

Table of Contents

Chapter 1 Device Overview

Chapter 2 Pins and Connections

Chapter 3 Power Management

Chapter 4 Memory Map

Chapter 5 Interrupt

Chapter 6 System Control

Chapter 7 Parallel Input/Output

Chapter 8 Clock Management

Chapter 9 Chip Configurations

Chapter 10 Central Processor Unit

Chapter 11 Keyboard Interrupts (KBI)

Chapter 12 Flextimer Module (FTM)

Chapter 13 8-Bit Modulo Timer (MTIM)

Chapter 14 Real-Time Counter (RTC)

Chapter 15 Serial Communications Interface (SCI)

Chapter 16 8-Bit Serial Peripheral Interface (8-Bit SPI)

Chapter 25 Introduction

Chapter 18 Memory Map/Register Definition

Chapter 21

Chapter 19

Chapter 20

Chapter 22

Related Products

Freescale Semiconductor Categories