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Address: 0xFC0B_C008 (SSI_RX0)
0xFC0B_C00C (SSI_RX1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 27-9. SSI Receive Data Registers (SSI_RX0, SSI_RX1)
Field
31–0
SSI receive data. SSI_RX0/1 are implemented as the first word of their respective Rx FIFOs. These bits receive data
SSI_RX
from RXSR depending on the mode of operation. If both FIFOs are in use, data is transferred to each data register
alternately. SSI_RX1 is only used in two-channel mode.
27.3.5
SSI Receive FIFO 0 and 1 Registers
The SSI receive FIFO registers are 15x32-bit registers and are not directly accessible. They always accept
data from the receive shift register (RXSR). If the associated interrupt is enabled, an interrupt is generated
when the data level in either of the SSI receive FIFOs reaches the selected threshold.
27.3.6
SSI Receive Shift Register (RXSR)
RXSR is a 24-bit shift register receiving incoming data from the SSI_RXD pin. This register is not directly
accessible. When a continuous clock is used, data is shifted in by the bit clock when the associated frame
sync is asserted. When a gated clock is used, data is shifted in by the gated clock. Data is assumed to be
received msb first if SSI_RCR[SHFD] is cleared. If this bit is set, the data is received lsb first. Data is
transferred to the appropriate SSI receive data register or receive FIFOs (if the receive FIFO is enabled and
the corresponding SSI_RX is full) after a word has been shifted in. For receiving less than 24 bits of data,
the lsb bits are appended with 0.
The following figures show the receiver loading and shifting operation. They illustrate some possible
values for WL, which can be extended for the other values.
Freescale Semiconductor
SSI_RX
Table 27-6. SSI_RX0/1 Field Descriptions
Description
Synchronous Serial Interface (SSI)
Access: User read/write
8
7
6
5
4
3
2
1
0
27-11
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