Functional Description - Freescale Semiconductor MCF54455 Reference Manual

Enhanced Direct Memory Access (eDMA)
Field
2 Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an
INT_HALF interrupt request by setting the appropriate bit in the EDMA_INT when the current major iteration count
reaches the halfway point. Specifically, the comparison performed by the eDMA engine is (CITER ==
(BITER >> 1)). This halfway point interrupt request is provided to support double-buffered (aka ping-pong)
schemes or other types of data movement where the processor needs an early indication of the transfer's
progress. The halfway complete interrupt disables when BITER values are less than two.
0 The half-point interrupt is disabled.
1 The half-point interrupt is enabled.
1 Enable an interrupt when major iteration count completes. If this flag is set, the channel generates an
INT_MAJOR interrupt request by setting the appropriate bit in the EDMA_INT when the current major iteration count
reaches zero.
0 The end-of-major loop interrupt is disabled.
1 The end-of-major loop interrupt is enabled.
0 Channel start. If this flag is set, the channel is requesting service. The eDMA hardware automatically clears
START this flag after the channel begins execution.
0 The channel is not explicitly started.
1 The channel is explicitly started via a software initiated service request.
19.5

Functional Description

This section provides an overview of the microarchitecture and functional operation of the eDMA module.
19.5.1 eDMA Microarchitecture
The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control
descriptor local memory. Additionally, the eDMA engine is further partitioned into four submodules:
• eDMA Engine
— Address Path:
This block implements registered versions of two channel transfer control descriptors,
channel x and channel y, and manages all master bus-address calculations. All the channels
provide the same functionality. This structure allows data transfers associated with one
channel to be preempted after the completion of a read/write sequence if a higher priority
channel activation is asserted while the first channel is active. After a channel is activated,
it runs until the minor loop is completed, unless preempted by a higher priority channel. This
provides a mechanism (enabled by DCHPRIn[ECP]) where a large data move operation can
be preempted to minimize the time another channel is blocked from execution.
When any channel is selected to execute, the contents of its TCD are read from local
memory and loaded into the address path channel x registers for a normal start and into
channel y registers for a preemption start. After the minor loop completes execution, the
address path hardware writes the new values for the TCDn_{SADDR, DADDR, CITER}
back to local memory. If the major iteration count is exhausted, additional processing are
performed, including the final address pointer updates, reloading the TCDn_CITER field,
and a possible fetch of the next TCDn from memory as part of a scatter/gather operation.
19-24
Table 19-30. TCDn_CSR Field Descriptions (continued)
Description
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