Freescale Semiconductor MCF54455 Reference Manual page 511

SDRAM Controller (SDRAMC)
Table 21-15. DDR2 Extended Mode Register (1) Field Descriptions (continued)
Field
A9–A7 OCD calibration program.
OCD program 000 OCD calibration mode exit; maintain setting
001 Drive (1)
010 Drive (0)
100 Adjust mode
111 OCD calibration default.
A6,A2 On die termination
R 00 ODT Disabled
tt
01 75 ohm
10 150 ohm
11 Reserved
A5–A3 Additive latency.
000 0
001 1
010 2
011 3
100 4
Else Reserved
A1 Output driver impedance control
0 Normal, Driver size of 100%
1 Weak, Driver size of 60%
A0 DLL enable
0 DLL Enable
1 DLL Disable
(RDQS
Enable)
0 (Disable)
0 (Disable)
1 (Enable)
1 (Enable)
21.5.1.6.6 DDR2 Extended Mode Register (2) and (3)
Figure 21-14 shows the extended mode register 2 and 3 used by DDR2 SDRAMs. This is the SDRAM's
extended mode register, and not the SDRAMC's mode/extended mode register (SDMR) described in
Section 21.4.1, "SDRAM Mode/Extended Mode Register
BA1 BA0
Field 1 0
21-24
Table 21-16. Strobe-Function Matrix
A11
A10 (DQS
Enable)
RDQS/DM
0 (Enable)
1 (Disable)
0 (Enable) RDQS
1 (Disable) RDQS
A12 A11 A10 A9
Figure 21-14. DDR2 Extended Mode Register 2
Description
Strobe Function Matrix
RDQS DQS
DM Hi-Z DQS
DM Hi-Z DQS
RDQS DQS
Hi-Z DQS
(SDMR)".
A8 A7 A6 A5
0
DQS
DQS
Hi-Z
DQS
Hi-Z
A4 A3 A2 A1
Freescale Semiconductor
A0