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Field
1
When this bit is set, FEC is enabled, and reception and transmission are possible. When this bit is cleared,
ETHER_EN
reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted
frame. The buffer descriptor(s) for an aborted transmit frame are not updated after clearing this bit. When
ETHER_EN is cleared, the DMA, buffer descriptor, and FIFO control logic are reset, including the buffer descriptor
and FIFO pointers. Hardware alters the ETHER_EN bit under the following conditions:
• ECRn[RESET] is set by software, in which case ETHER_EN is cleared
• An error condition causes the EIRn[EBERR] bit to set, in which case ETHER_EN is cleared
0
When this bit is set, the equivalent of a hardware reset is performed but it is local to the FEC. ECRn[ETHER_EN]
RESET
is cleared and all other FEC registers take their reset values. Also, any transmission/reception currently in progress
is abruptly aborted. This bit is automatically cleared by hardware during the reset sequence. The reset sequence
takes approximately eight internal bus clock cycles after this bit is set.
26.4.7
MII Management Frame Registers (MMFR0 & MMFR1)
The MMFRn is user-accessible and does not reset to a defined value. The MMFRn registers are used to
communicate with the attached MII compatible PHY device(s), providing read/write access to their MII
registers. Performing a write to the MMFRn causes a management frame to be sourced unless the MSCRn
is programmed to 0. If MSCRn is cleared while MMFRn is written and then MSCRn is written with a
non-zero value, an MII frame is generated with the data previously written to the MMFRn. This allows
MMFRn and MSCRn to be programmed in either order if MSCRn is currently zero.
Address: 0xFC03_0040 (MMFR0)
0xFC03_4040 (MMFR1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
ST
OP
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Field
31–30
Start of frame delimiter. These bits must be programmed to 0b01 for a valid MII management frame.
ST
29–28
Operation code.
OP
00 Write frame operation, but not MII compliant.
01 Write frame operation for a valid MII management frame.
10 Read frame operation for a valid MII management frame.
11 Read frame operation, but not MII compliant.
27–23
PHY address. This field specifies one of up to 32 attached PHY devices.
PA
22–18
Register address. This field specifies one of up to 32 registers within the specified PHY device.
RA
Freescale Semiconductor
Table 26-9. ECRn Field Descriptions (continued)
PA
RA
Figure 26-7. MII Management Frame Register (MMFRn)
Table 26-10. MMFRn Field Descriptions
Fast Ethernet Controllers (FEC0 and FEC1)
Description
TA
Description
Access: User read/write
8
7
6
5
4
3
2
1
0
DATA
26-16
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