Freescale Semiconductor MCF54455 Reference Manual page 505

SDRAM Controller (SDRAMC)
Function
Row and Bank Active
Read
Write
Burst Terminate (DDR only)
Precharge All Banks
Precharge Selected Bank
Load Mode Register
Load Extended Mode Register
Auto Refresh
Self Refresh
Power Down
Deep Power-Down
Many commands require a delay before the next command may be issued; sometimes the delay depends
on the type of the next command. These delay requirements are managed by the values programmed in the
memory controller configuration registers (SDCFG1, SDCFG2).
21.5.1.1 Row and Bank Active Command (
The command is responsible for latching the row and bank address and activating the specified row
ACTV
bank of a memory block. After the row is activated, it can be accessed using subsequent read and write
commands.
The SDRAMC supports one active row for each chip select block. See
Section 21.6.4, "Page Management,"
21.5.1.2 Read Command (
When the SDRAMC receives a read request via the internal bus, it first checks the row and bank of the
new access. If the address falls within the active row of an active bank, it is a page hit, and the read is issued
as soon as possible (pending any delays required by previous commands). If the address is within an
inactive bank, the memory controller issues an ACTV followed by the read command. If the address is not
within the active row of an active bank, the memory controller issues a pre command to close the active
row. Then, the SDRAMC issues ACTV to activate the necessary row and bank for the new access,
followed by the read to the SDRAM.
21-18
Table 21-10. SDRAM Commands (continued)
Symbol CKE CS
H L
ACTV
H L
READ
H L
WRITE
H L
BST
H L
PALL
H L
PRE
H L
LMR
H L
LEMR
H L
REF
HL L
SREF
HL H
PDWN
L L
DPD
H = High
L = Low
V = Valid
X = Don't care
NOTE
for more information.
)
READ
RAS CAS WE BA[1:0]
L H H V
H L H V
H L L V
H H L X
L H L X
L H L V
L L L LL
L L L LH
L L H X
L L H X
X X X X
H H L X
)
ACTV
A[10] Other A
V V
L V
L V
X X
H X
L X
V V
V V
X X
X X
X X
X X
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