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27.3.8
SSI Interrupt Status Register (SSI_ISR)
The SSI interrupt status register monitors the SSI. This register is read-only and is used by the processor
to interrogate the status of the SSI module. All receiver-related interrupts are generated only if the receiver
is enabled (SSI_CR[RE] = 1). Likewise, all transmitter-related interrupts are generated only if the
transmitter is enabled (SSI_CR[TE] = 1).
Refer to
Section 27.4.6, "Transmit Interrupt Enable Bit Description,"
details on SSI interrupt generation.
All flags in the SSI_ISR are updated after the first bit of the next SSI word
has completed transmission or reception. Some status bits (ROE0/1 and
TUE0/1) are cleared by reading the SSI_ISR followed by a read or write to
the SSI_RX0/1 or SSI_TX0/1 registers.
Address: 0xFC0B_C014 (SSI_ISR)
31
30
29
R
0
0
0
W
Reset
0
0
0
15
14
13
R RDR1 RDR0 TDE1 TDE0 ROE1 ROE0 TUE1 TUE0 TFS
W
Reset
0
0
1
Field
31–19
Reserved, must be cleared.
18
AC97 command address register updated. This bit causes the command address updated interrupt when the
CMDAU
SSI_IER[CMDAU] bit is set. This status bit is set each time there is a difference in the previous and current value
of the received command address. This bit is cleared upon reading the SSI_ACADD register.
0 No change in SSI_ACADD register
1 SSI_ACADD register updated with different value
17
AC97 command data register updated. This bit causes the command data updated interrupt when the
CMDU
SSI_IER[CMDDU] bit is set. This status bit is set each time there is a difference in the previous and current value
of the received command data. This bit is cleared upon reading the SSI_ACDAT register.
0 No change in SSI_ACDAT register
1 SSI_ACDAT register updated with different value
16
AC97 receive tag updated. This status bit is set each time there is a difference in the previous and current value
RXT
of the received tag. It causes the receive tag interrupt if the SSI_IER[RXT] bit is set. This bit is cleared upon reading
the SSI_ATAG register.
0 No change in SSI_ATAG register
1 SSI_ATAG register updated with different value
Freescale Semiconductor
Section 27.4.5, "Receive Interrupt Enable Bit Description,"
28
27
26
25
0
0
0
0
0
0
0
0
12
11
10
9
1
0
0
0
Figure 27-15. SSI Interrupt Status Register (SSI_ISR)
Table 27-8. SSI_ISR Field Descriptions
NOTE
24
23
22
21
0
0
0
0
0
0
0
0
8
7
6
5
RFS
TLS
0
0
0
0
Description
Synchronous Serial Interface (SSI)
and
for more
Access: User read-only
20
19
18
17
0
0
CMDAU CMDDU RXT
0
0
0
0
4
3
2
1
RLS RFF1
RFF0
TFE1
0
0
0
1
16
0
0
TFE0
1
27-15
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