Freescale Semiconductor MCF54455 Reference Manual page 204

9.3.4.18 Programmable Interrupt Timers (PIT0–3)
In stop mode (or doze mode, if so programmed in the PCSRn register), the programmable interrupt timer
(PIT) ceases operation, and freezes at the current value. When exiting these modes, the PIT resumes
operation from the stopped value. It is the responsibility of software to avoid erroneous operation.
When not stopped, the PIT may generate an interrupt to exit the low-power modes.
9.3.4.19 DMA Timers (DTIM0–3)
In wait and doze modes, the DMA timers may generate an interrupt to exit a low-power mode. This
interrupt can generate when the DMA timer is in input capture mode or reference compare mode.
In input capture mode, where the capture enable (CE) field of the timer mode register (DTMR) has a
non-zero value and the DTXMR[DMAEN] is cleared, an interrupt issues upon a captured input. In
reference compare mode, where the output reference requests interrupt enable (ORRI) bit of DTMR is set
and DTXMR[DMAEN] is cleared, an interrupt issues when the timer counter reaches the reference value.
DMA timer operation disables in stop mode. Upon exiting stop mode, the timer resumes operation unless
stop mode was exited by reset.
9.3.4.20 DMA Serial Peripheral Interface (DSPI)
In wait and doze modes, the DSPI module is unaffected and may generate an interrupt to exit these
low-power modes.
In stop mode, the DSPI stops immediately and freezes operation, register values, state machines, and
external pins. During this mode, the DSPI clocks shut down. Coming out of stop mode returns the DSPI
to operation from the state prior to stop mode entry.
9.3.4.21 UART Modules (UART0–2)
In wait and doze modes, the UARTs are unaffected and may generate an interrupt to exit these low-power
modes.
In stop mode, the UARTs stop immediately and freeze their operation, register values, state machines, and
external pins. During this mode, the UART clocks shut down. Exiting stop mode returns the UARTs to the
operation of the state prior to stop-mode entry.
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9.3.4.22 I C Module
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When the I C Module is enabled by the setting of the I2CR[IEN] bit and the device is not in stop mode,
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the I C module is operable and may generate an interrupt to bring the device out of a low-power mode.
For an interrupt to occur, the I2CR[IIE] bit must be set to enable interrupts, and the setting of the I2SR[IIF]
generates the interrupt signal to the CPU and interrupt controller. The setting of I2SR[IIF] signifies the
completion of one byte transfer or the reception of a calling address matching its own specified address
when in slave-receive mode.
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In stop mode, the I C module stops immediately and freezes operation, register values, and external pins.
Upon exiting stop mode, the I
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C resumes operation unless stop mode was exited by reset.
Power Management
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