Table of Contents
Advertisement
Continuous
SSI_BCLK
SSI_FS
Early
SSI_FS
Gated
SSI_BCLK
SSI_TXD
SSI_RXD
Bit Length Frame Sync
Word Length Frame Sync
SSI_CR
[SYN]
27.3
Memory Map/Register Definition
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
Address
0xFC0B_C000 SSI Transmit Data Register 0 (SSI_TX0)
0xFC0B_C004 SSI Transmit Data Register 1 (SSI_TX1)
0xFC0B_C008 SSI Receive Data Register 0 (SSI_RX0)
0xFC0B_C00C SSI Receive Data Register 1 (SSI_RX1)
0xFC0B_C010 SSI Control Register (SSI_CR)
0xFC0B_C014 SSI Interrupt Status Register (SSI_ISR)
Freescale Semiconductor
7
6
5
4
3
8-bit Data
7
6
5
4
3
Figure 27-3. Serial Clock and Frame Sync Timing
Table 27-3. Clock and Frame Sync Pin Configuration
SSI_RCR
[RXDIR]
TXDIR
Synchronous Mode
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
1
Table 27-4. SSI Memory Map
Register
2
1
0
2
1
0
SSI_TCR
SSI_BCLK
TFDIR
0
Bit clock in
1
Bit clock in
0
Bit clock out
1
Bit clock out
x
Gated clock in
x
Gated clock out
Width
Access Reset Value
(bits)
32
32
32
32
32
32
Synchronous Serial Interface (SSI)
7
6
7
6
SSI_FS
FS in
FS out
FS in
FS out
—
—
Section/Page
R/W
0x0000_0000
27.3.1/27-8
R/W
0x0000_0000
27.3.1/27-8
R
0x0000_0000
27.3.4/27-10
R
0x0000_0000
27.3.4/27-10
R/W
0x0000_0000
27.3.7/27-13
R
0x0000_3003
27.3.8/27-15
27-7
Advertisement
Table of Contents
