Freescale Semiconductor MCF54455 Reference Manual page 768

Field
31 Transfer complete flag. Indicates all bits in a frame have been shifted out. The TCF bit is set after the last incoming
TCF databit is sampled, but before the t
= 0)" for details. The TCF bit is cleared by writing 1 to it.
0 Transfer not complete
1 Transfer complete
30 TX and RX status. Reflects the status of the DSPI. See
TXRXS information on what causes this bit to be cleared or set.
0 TX and RX operations are disabled (DSPI is in stopped state)
1 TX and RX operations are enabled (DSPI is in running state)
29 Reserved, must be cleared.
28 End of queue flag. Indicates transmission in progress is the last entry in a queue. The EOQF bit is set when the TX
EOQF FIFO entry has the EOQ bit set in the command halfword and after the last incoming databit is sampled, but before
the t delay starts. Refer to
ASC
The EOQF bit is cleared by writing 1 to it. When the EOQF bit is set, the TXRXS bit is automatically cleared.
0 EOQ is not set in the executing SPI command
1 EOQ bit is set in the executing SPI command
Note: EOQF does not function in slave mode.
27 Transmit FIFO underflow flag. Indicates that an underflow condition in the TX FIFO has occurred. The transmit
TFUF underflow condition is detected only for DSPI modules operating in slave mode. The TFUF bit is set when the TX
FIFO of a DSPI operating in slave mode is empty, and a transfer is initiated by an external SPI master. The TFUF bit
is cleared by writing 1 to it.
0 TX FIFO underflow has not occurred
1 TX FIFO underflow has occurred
26 Reserved, must be cleared.
25 Transmit FIFO fill flag. Indicates that the TX FIFO can be filled. Provides a method for the DSPI to request more
TFFF entries to be added to the TX FIFO. The TFFF bit is set while the TX FIFO is not full. Therefore, this bit is set after
DSPI_MCR[MDIS] is cleared after a reset. The TFFF bit can be cleared by writing 1 to it or by an acknowledgement
from the eDMA controller when the TX FIFO is full.
0 TX FIFO is full
1 TX FIFO is not full
24–20 Reserved, must be cleared.
19 Receive FIFO overflow flag. Indicates that an overflow condition in the RX FIFO has occurred. The bit is set when
RFOF the RX FIFO and shift register are full and a transfer is initiated. The bit is cleared by writing 1 to it.
0 RX FIFO overflow has not occurred
1 RX FIFO overflow has occurred
18 Reserved, must be cleared.
17 Receive FIFO drain flag. Indicates that the RX FIFO can be drained. Provides a method for the DSPI to request that
RFDF entries be removed from the RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be cleared
by writing 1 to it or by an acknowledgement from the eDMA controller when the RX FIFO is empty.
0 RX FIFO is empty
1 RX FIFO is not empty
Note: In the interrupt service routine, RFDF must be cleared only after the DSPI_POPR register is read.
16 Reserved, must be cleared.
Freescale Semiconductor
Table 31-6. DSPI_SR Field Descriptions
Description
delay starts. Refer to
ASC
Section 31.4.4.1, "Classic SPI Transfer Format (CPHA =
DMA Serial Peripheral Interface (DSPI)
Section 31.4.4.1, "Classic SPI Transfer Format (CPHA
Section 31.4.1, "Start and Stop of DSPI Transfers" for
0)" for details.
31-15