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Field
6–5
Cache mode. Selects the cache mode and access precision. Precise and imprecise modes are described in
CM
Section 6.4.1.2, "Cache-Inhibited
00 Cacheable, write-through
01 Cacheable, copyback
10 Cache-inhibited, precise
11 Cache-inhibited, imprecise
4
Reserved, must be cleared.
3
Supervisor protect.
SP
0 Indicates supervisor and user mode access allowed
1 Indicates only supervisor access is allowed to this address space and attempted user mode accesses
generate an access error exception
2
Write protect. Selects the write privilege of the memory region. This field is reserved in the instruction attribute
W
ACRs (ACR2–3).
0 Read and write accesses permitted
1 Write accesses not permitted
1–0
Reserved, must be cleared.
6.4
Functional Description
Figure 6-6
shows the general flow of a caching operation using the 16-Kbyte data cache as an example.
This chapter assumes a data cache. Instruction cache operations are similar except for writing to the cache
has no support; therefore, such notions of modified cache lines and write allocation do not apply.
Freescale Semiconductor
Table 6-4. ACRn Field Descriptions (continued)
Description
Accesses."
Cache
6-9
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