Freescale Semiconductor MCF54455 Reference Manual page 358

Table 16-4. Pin Multiplexing and Control Memory Map (continued)
Address
0xFC0A_4019 PDDR_FEC0L
0xFC0A_401A PDDR_SSI
0xFC0A_401B PDDR_FBCTL
0xFC0A_401C PDDR_BE
0xFC0A_401D PDDR_CS
0xFC0A_401E PDDR_DMA
0xFC0A_401F PDDR_FECI2C
0xFC0A_4021 PDDR_UART
0xFC0A_4022 PDDR_DSPI
0xFC0A_4023 PDDR_TIMER
0xFC0A_4024 PDDR_PCI
0xFC0A_4025 PDDR_USB
0xFC0A_4026 PDDR_ATAH
0xFC0A_4027 PDDR_ATAL
0xFC0A_4028 PDDR_FEC1H
0xFC0A_4029 PDDR_FEC1L
0xFC0A_402C PDDR_FBADH
0xFC0A_402D PDDR_FBADMH
0xFC0A_402E PDDR_FBADML
0xFC0A_402F PDDR_FBADL
0xFC0A_4030 PPDSDR_FEC0H
0xFC0A_4031 PPDSDR_FEC0L
0xFC0A_4032 PPDSDR_SSI
0xFC0A_4033 PPDSDR_FBCTL
0xFC0A_4034 PPDSDR_BE
0xFC0A_4035 PPDSDR_CS
0xFC0A_4036 PPDSDR_DMA
0xFC0A_4037 PPDSDR_FECI2C
0xFC0A_4039 PPDSDR_UART
0xFC0A_403A PPDSDR_DSPI
0xFC0A_403B PPDSDR_TIMER
Freescale Semiconductor
Register
Port Pin Data/Set Data Registers
Pin Multiplexing and Control
Width
Access Reset Value
(bits)
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W 0x00
8 R/W See Section
8 R/W See Section
8 R/W See Section
8 R/W See Section
8 R/W See Section
8 R/W See Section
8 R/W See Section
8 R/W See Section
8 R/W See Section
8 R/W See Section
8 R/W See Section
Section/Page
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.2/16-18
16.3.3/16-20
16.3.3/16-20
16.3.3/16-20
16.3.3/16-20
16.3.3/16-20
16.3.3/16-20
16.3.3/16-20
16.3.3/16-20
16.3.3/16-20
16.3.3/16-20
16.3.3/16-20
16-13