Freescale Semiconductor MCF54455 Reference Manual page 782

DSPI_SCK
(CPOL = 0)
DSPI_SCK
(CPOL = 1)
Master and Slave
Sample
Master DSPI_SOUT/
Slave DSPI_SIN
Master DSPI_SIN/
Slave DSPI_SOUT
DSPI_PCSn/SS
MSB First (LSBFE = 0):
LSB First (LSBFE = 1):
t = PCS to SCK delay.
CSC
t = After SCK delay.
ASC
t = Delay after transfer (minimum CS idle time).
DT
Figure 31-15. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 0, FMSZ = 8)
The master initiates the transfer by placing its first data bit on the DSPI_SOUT pin and asserting the
appropriate peripheral chip select signals to the slave device. The slave responds by placing its first data
bit on its DSPI_SOUT pin. After the t
The master and slave devices use this edge to sample the first input data bit on their serial data input
signals. At the second edge of the DSPI_SCK, the master and slave devices place their second data bit on
their serial data output signals. For the rest of the frame, the master and the slave sample their DSPI_SIN
pins on the odd-numbered clock edges and change the data on their DSPI_SOUT pins on the
even-numbered clock edges. After the last clock edge occurs, a delay of t
negates the DSPI_PCSn signals. A delay of t
the master.
If DSPI_CTARn[CPHA] is cleared:
• At the next to last serial clock edge of the frame (edge 15 of
— Master's TCF and EOQF are set and RXCTR counter is updated
• At the last serial clock edge of the frame (edge 16 of
— Slave's TCF is set and RXCTR counter is updated
31.4.4.2 Classic SPI Transfer Format (CPHA = 1)
The transfer format shown in
the first DSPI_SCK edge before the first data bit becomes available on the slave DSPI_SOUT pin. In this
format, the master and slave devices change the data on their DSPI_SOUT pins on the odd-numbered
DSPI_SCK edges and sample the data on their DSPI_SIN pins on the even-numbered DSPI_SCK edges.
Freescale Semiconductor
Master (CPHA = 0): TCF and EOQF are set and RXCTR counter
is updated at next to last DSPI_SCK edge of frame (edge 15)
Slave (CPHA = 0): TCF is set and RXCTR counter is updated at
last DSPI_SCK edge of frame (edge 16)
1 2 3 4 5
t
CSC
MSB Bit 6 Bit 5
LSB Bit 1 Bit 2
delay elapses, the master outputs the first edge of DSPI_SCK.
CSC
is inserted before a new frame transfer can be initiated by
DT
Figure 31-16 communicates with peripheral SPI slave devices that require
6 7 8 9 10 11 12 13 14
Bit 4 Bit 3 Bit 2 Bit 1
Bit 3 Bit 4 Bit 5 Bit 6
ASC
Figure
Figure 31-15)
DMA Serial Peripheral Interface (DSPI)
15 16
t
ASC
t
DT
t
CSC
LSB
MSB
is inserted before the master
31-15)
31-29