Freescale Semiconductor MCF5329 Manuals

Freescale Semiconductor MCF5329 Manuals

Manuals and User Guides for Freescale Semiconductor MCF5329. We have 1 Freescale Semiconductor MCF5329 manual available for free PDF download: Reference Manual

Freescale Semiconductor MCF5329 Reference Manual

Freescale Semiconductor MCF5329 Reference Manual (924 pages)

Devices Supported: MCF5327; MCF5328; MCF53281; MCF5329

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 16 MB

Table of Contents

Table of Contents
5
Paragraph Number

6
- About this Book
  29
- Audience
  29
- Organization
  29
- Suggested Reading
  32
  - Hardware Specification
    32
  - General Information
    33
  - Coldfire Documentation
    33
  - Conventions
    33
  - Register Figure Conventions
    34
  - Acronyms and Abbreviations
    35
  - Terminology Conventions
    36
Chapter 1 Overview

39
- Mcf532X Device Configurations
  39
- Block Diagram
  40
- Features
  41
  - Overview
    42
  - V3 Core Overview
    46
  - Debug Module
    47
  - Jtag
    47
  - On-Chip Memories
    47
  - LCD Controller
    48
  - Voice-Over-IP (Voip) System Solution
    48
  - SDR/DDR SDRAM Controller
    49
  - USB Host and OTG Controllers
    49
  - Synchronous Serial Interface (SSI)
    50
  - Fast Ethernet Controller (FEC)
    50
  - Cryptography Accelerators
    50
  - Flexcan
    51
  - Uarts
    51
  - I 2 C Bus
    51
  - Qspi
    51
  - Pulse Width Modulation (PWM) Timer
    51
  - Real Time Clock
    51
  - DMA Timers (DTIM0-DTIM3)
    51
  - Software Watchdog Timer
    52
  - Periodic Interrupt Timers (PIT0-PIT3)
    52
  - Clock Module and Phase Locked Loop (PLL)
    52
  - Interrupt Controllers
    52
  - DMA Controller
    52
  - Flexbus External Interface
    53
  - Reset Controller Module
    53
  - Gpio
    53
- Documentation
  54
- Signal Descriptions
  55
Chapter 14 Introduction

55
- Signal Properties Summary
  55
  - Internal Pull-Up/Pull-Downs Resistors
    62
- Signal Primary Functions
  63
  - Reset Signals
    63
  - PLL and Clock Signals
    63
  - Mode Selection
    64
  - Flexbus Signals
    65
  - SDRAM Controller Signals
    66
  - External Interrupt Signals
    66
  - DMA Signals
    66
  - LCD Controller Signals
    67
  - Ethernet Module (FEC) Signals
    67
  - I2C I/O Signals
    68
  - Flexcan Signals
    69
  - Queued Serial Peripheral Interface (QSPI)
    69
  - Synchronous Serial Interface (SSI) Signals
    69
  - Universal Serial Bus (USB) Signals
    70
  - Pulse Width Modulation (PWM) Module Signals
    70
  - UART Module Signals
    71
  - DMA Timer Signals
    71
  - Debug Support Signals
    71
  - Test Signals
    73
  - Power and Ground Pins
    73
- External Boot Mode
  74
Chapter 3 Coldfire Core

75
- Introduction
  75
  - Overview
    75
- Memory Map/Register Description
  78
- Functional Description
  84
Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC)

107
- Introduction
  107
  - Overview
    107
- Memory Map/Register Definition
  109
- Functional Description
  114
  - Fractional Operation Mode
    116
  - EMAC Instruction Set Summary
    118
  - EMAC Instruction Execution Times
    119
  - Data Representation
    120
  - MAC Opcodes
    120
    
    Introduction
    127
    
    Memory Map/Register Definition
    128
Chapter 5

130
- Access Control Registers (ACR0–ACR1)
  130
- Functional Description
  131
- Cache Operation
  133
- Caching Modes
  136
- Cache-Inhibited Accesses
  137
  - Read Miss
    138
  - Read Hit
    138
- Cache Coherency
  139
- Cache Locking
  141
- Cache Management
  142
- Cache Operation Summary
  143
  - Introduction
    149
  - Memory Map/Register Description
    150
  - Initialization/Application Information
    152
Chapter 8 Power Management

153
- Introduction
  155
- Block Diagram
  157
- Memory Map/Register Definition
  159
- PLL Output Divider Register (PODR)
  160
- PLL Modulation Divider Register (PMDR)
  161
- PLL Feedback Divider Register (PFDR)
  162
- Dithering Waveform Definition
  163
- PLL Frequency Multiplication Factor Select
  164
- System Clock Modes
  165
  - External Reset
    166
  - Introduction
    167
- Wake-Up Control Register
  168
  - Peripheral Power Management Set Registers (PPMSR0 & PPMSR1)
    169
  - Peripheral Power Management Clear Registers (PPMCR0 & PPMCR1)
    170
- Low-Power Control Register (LPCR)
  173
- Functional Description
  174
- Low-Power Modes
  175
- Peripheral Behavior in Low-Power Modes
  176
- Summary of Peripheral State During Low-Power Modes
  181
  - Introduction
    185
  - External Signal Descriptions
    186
- Chip Configuration Register (CCR)
  187
- Reset Configuration Register (RCON)
  188
- Miscellaneous Control Register (MISCCR)
  189
- Clock Divider Register
  190
- USB Host Controller Status Register (UHCSR)
  191
- Functional Description
  193
- PLL Mode Selection
  195
- Chip Select Configuration
  196
  - Introduction
    197
  - External Signal Description
    198
Chapter 10

199
- Reset Status Register (RSR)
  199
- Functional Description
  200
- Reset Control Flow
  201
- Concurrent Resets
  203
  - Introduction
    205
  - Memory Map/Register Definition
    206
Chapter 11

207
- Master Privilege Register 0 (MPR0)
  207
- Master Privilege Register 1 (MPR1)
  208
- Core Watchdog Service Register (CWSR)
  213
- SCM Interrupt Status Register (SCMISR)
  214
- Core Fault Address Register (CFADR)
  215
- Core Fault Interrupt Enable Register (CFIER)
  216
- Core Fault Data Register (CFDTR)
  217
- Functional Description
  218
- Core Data Fault Recovery Registers
  219
  - Overview
    221
  - Features
    223
- Arbitration
  226
  - Initialization/Application Information
    227
  - Introduction
    229
  - Overview
    230
  - Features
    231
  - Memory Map/Register Definition
    239
  - Overview
    266
  - Initialization/Application Information
    267
  - Introduction
    269
  - Memory Map/Register Definition
    270
  - Saved Level Mask Register (SLMASK)
    278
  - Interrupt Sources
    280
  - Software and Level 1 - 7 IACK Registers (Swiackn, L1Iackn - L7Iackn)
    283
- Functional Description
  284
- Initialization/Application Information
  287
  - Interrupt Service Routines
    287
Chapter 15 Edge Port Module (EPORT)

289
- Introduction
  289
- Low-Power Mode Operation
  290
- Interrupt/Gpio Pin Descriptions
  290
- Memory Map/Register Definition
  290
Chapter 16 Enhanced Direct Memory Access (Edma)

295
- Overview
  295
- Block Diagram
  295
- Features
  296
- Modes of Operation
  296
  - Normal Mode
    296
  - Debug Mode
    297
- External Signal Description
  297
  - External Signal Timing
    297
- Memory Map/Register Definition
  298
- Functional Description
  318
  - Edma Microarchitecture
    318
  - Edma Basic Data Flow
    319
- Initialization/Application Information
  322
  - Edma Initialization
    322
  - DMA Programming Errors
    325
  - DMA Arbitration Mode Considerations
    325
  - DMA Transfer
    326
  - Edma Tcdn Status Monitoring
    329
  - Channel Linking
    330
  - Dynamic Programming
    331
Chapter 17 Flexbus

333
- Introduction
  333
  - Overview
    333
  - Features
    334
- External Signals
  334
  - Address and Data Buses (FB_A[23:0], FB_D[31:0])
    334
  - Chip Selects (FB_CS[5:0])
    335
  - Byte Enables/Byte Write Enables (FB_BE/BWE[3:0])
    335
  - Output Enable (FB_OE)
    335
  - Read/Write (FB_R/W)
    335
  - Transfer Start (FB_TS)
    335
  - Transfer Acknowledge (FB_TA)
    335
- Memory Map/Register Definition
  336
- Functional Description
  341
  - Chip-Select Operation
    341
  - Data Transfer Operation
    342
  - Data Byte Alignment and Physical Connections
    343
  - Bus Cycle Execution
    344
  - Flexbus Timing Examples
    345
    
    Basic Write Bus Cycle
    347
    
    Timing Variations
    351
  - Burst Cycles
    356
  - Misaligned Operands
    362
  - Bus Errors
    362
Chapter 18 SDRAM Controller (SDRAMC)

363
- Introduction
  363
  - Block Diagram
    364
  - Features
    364
  - Terminology
    365
- External Signal Description
  365
- Interface Recommendations
  367
  - Supported Memory Configurations
    367
  - SDRAM SDR Connections
    372
  - SDRAM DDR Component Connections
    374
  - DDR SDRAM Layout Considerations
    374
  - Termination Example
    375
- Memory Map/Register Definition
  376
  - SDRAM Mode/Extended Mode Register (SDMR)
    376
  - SDRAM Control Register (SDCR)
    377
  - SDRAM Configuration Register 1 (SDCFG1)
    379
  - SDRAM Configuration Register 2 (SDCFG2)
    381
  - SDRAM Chip Select Configuration Registers
    382
  - SDRAM Commands
    383
  - Functional Description
    383
  - Read Clock Recovery (RCR) Block
    388
- Initialization/Application Information
  389
  - Page Management
    390
  - Transfer Size
    391
Chapter 19 Fast Ethernet Controller (FEC)

393
- Introduction
  393
  - Overview
    393
  - Block Diagram
    393
  - Features
    395
- Modes of Operation
  396
  - Full and Half Duplex Operation
    396
  - Interface Options
    396
  - Address Recognition Options
    397
  - Internal Loopback
    397
- External Signal Description
  397
- Memory Map/Register Definition
  398
- Functional Description
  417
  - Buffer Descriptors
    417
  - Initialization Sequence
    422
  - User Initialization (Prior to Setting ECR[ETHER_EN])
    422
  - Microcontroller Initialization
    423
  - Network Interface Options
    424
  - User Initialization (after Setting ECR[ETHER_EN])
    424
  - FEC Frame Transmission
    425
  - FEC Frame Reception
    426
  - Ethernet Address Recognition
    427
  - 19.5.10 Hash Algorithm
    429
  - 19.5.11 Full Duplex Flow Control
    432
  - 19.5.12 Inter-Packet Gap (IPG) Time
    433
  - 19.5.13 Collision Managing
    433
  - 19.5.14 MII Internal and External Loopback
    433
  - 19.5.15 Ethernet Error-Managing Procedure
    433
Chapter 20 Universal Serial Bus Interface - Host Module

437
- Introduction
  437
  - Block Diagram
    438
  - Overview
    438
  - Features
    438
  - Modes of Operation
    439
- External Signal Description
  439
  - USB Host Control and Status Signals
    440
    
    Memory Map/Register Definitions
    441
    
    Functional Description
    442
Chapter 21 Universal Serial Bus Interface - On-The-Go Module

443
- Introduction
  443
  - Overview
    443
  - Block Diagram
    444
  - Features
    445
  - Modes of Operation
    446
- External Signal Description
  447
  - USB OTG Control and Status Signals
    448
- Memory Map/Register Definition
  450
  - Module Identification Registers
    451
  - Capability Registers
    455
  - Operational Registers
    458
    
    Functional Description
    487
    
    Initialization/Application Information
    488
  - Device Data Structures
    489
  - Device Operation
    496
  - Servicing Interrupts
    514
  - Deviations from the EHCI Specifications
    515
    
    Introduction
    521
    
    External Signal Description
    523
- LCDC Screen Start Address Register (LCD_SSAR)
  525
- LCDC Cursor Position Register (LCD_CPR)
  526
- LCDC Cursor Width Height and Blink Register (LCD_CWHB)
  527
- LCDC Color Cursor Mapping Register (LCD_CCMR)
  528
- LCDC Panel Configuration Register (LCD_PCR)
  529
- LCDC Horizontal Configuration Register (LCD_HCR)
  532
- LCDC Panning Offset Register (LCD_POR)
  533
- LCDC Sharp Configuration Register (LCD_SCR)
  534
- LCDC PWM Contrast Control Register (LCD_PCCR)
  536
- LCDC Refresh Mode Control Register (LCD_RMCR)
  537
- LCDC Interrupt Configuration Register (LCD_ICR)
  538
- LCDC Interrupt Enable Register (LCD_IER)
  539
- LCDC Interrupt Status Register (LCD_ISR)
  540
- LCDC Graphic Window Start Address Register (LCD_GWSAR)
  542
- LCDC Graphic Window Virtual Page Width Register (LCD_GWVPW)
  543
- LCDC Graphic Window Position Register (LCD_GWPR)
  544
- LCDC Graphic Window DMA Control Register (LCD_GWDCR)
  546
- Functional Description
  549
- Graphic Window on Screen
  550
- Panning
  551
- Black-And-White Operation
  553
- Color Generation
  554
- Frame Rate Modulation Control (FRC)
  556
- Panel Interface Signals and Timing
  557
- Bpp Mode Color STN Panel
  560
  - Introduction
    565
  - The Can System
    566
  - Features
    567
  - External Signal Description
    569
Chapter 23

570
- Flexcan Configuration Register (CANMCR)
  570
- Flexcan Control Register (CANCTRL)
  572
- Flexcan Free Running Timer Register (TIMER)
  574
- Rx Mask Registers (RXGMASK, RX14MASK, RX15MASK)
  575
- Flexcan Error Counter Register (ERRCNT)
  576
- Flexcan Error and Status Register (ERRSTAT)
  577
- Interrupt Mask Register (IMASK)
  579
- Interrupt Flag Register (IFLAG)
  580
- Functional Overview
  584
- Arbitration Process
  585
- Matching Process
  587
- CAN Protocol Related Frames
  589
- Time Stamp
  590
- Initialization/Application Information
  592
- Interrupts
  593
- Introduction
  595
Chapter 36

596
Chapter 29

645
- Introduction
  645
- Features
  646
- External Signal Description
  647
- RTC Seconds Counter Register (RTC_SECONDS)
  648
- RTC Seconds Alarm Register (RTC_ALRM_SEC)
  649
- RTC Interrupt Status Register (RTC_ISR)
  650
- RTC Interrupt Enable Register (RTC_IER)
  651
- RTC Stopwatch Minutes Register (RTC_STPWCH)
  652
- RTC Days Counter Register (RTC_DAYS)
  653
- Functional Description
  654
- Sampling Timer
  655
- Initialization/Application Information
  656
- Introduction
  657
- Memory Map/Register Definition
  658
Chapter 26

659
- PWM Enable Register (PWME)
  659
- PWM Polarity Register (PWMPOL)
  660
- PWM Prescale Clock Select Register (PWMPRCLK)
  661
- PWM Center Align Enable Register (PWMCAE)
  662
- PWM Scale a Register (PWMSCLA)
  663
- PWM Scale B Register (PWMSCLB)
  664
  - PWM Channel Counter Registers (PWMCNT N )
    665
  - PWM Channel Period Registers (PWMPER N )
    666
- PWM Shutdown Register (PWMSDN)
  667
- Functional Description
  668
  - PWM Channel Timers
    670
  - Introduction
    679
Chapter 22

680
- Block Diagram
  680
Chapter 27

681
Chapter 28

690
- Set-And-Forget Timer Operation
  690
- Timeout Specifications
  691
  - Introduction
    693
  - Features
    694
  - Memory Map/Register Definition
    695
  - DMA Timer Extended Mode Registers (DTXMR N )
    696
  - DMA Timer Event Registers (DTER N )
    697
  - DMA Timer Reference Registers (DTRR N )
    698
  - DMA Timer Capture Registers (DTCR N )
    699
  - DMA Timer Counters (DTCN N )
    700
- Output Mode
  701
- Calculating Time-Out Values
  702
- Introduction
  705
Chapter 32

706
- Overview
  706
- Memory Map/Register Definition
  707
Chapter 30

709
- QSPI Delay Register (QDLYR)
  709
- QSPI Wrap Register (QWR)
  710
- QSPI Address Register (QAR)
  711
- QSPI Data Register (QDR)
  712
- Functional Description
  713
- Qspi Ram
  715
- Baud Rate Selection
  716
- Transfer Delays
  717
- Transfer Length
  718
  - Initialization/Application Information
    719
  - Introduction
    721
  - Features
    722
  - External Signal Description
    723
Chapter 31

736
- Transmitter/Receiver Clock Source
  736
- Transmitter and Receiver Operating Modes
  738
- Looping Modes
  742
- Multidrop Mode
  744
- Bus Operation
  746
- UART Module Initialization Sequence
  748
  - Introduction
    755
  - Overview
    756
  - Memory Map/Register Definition
    757
  - Functional Description
    761
- Slave Address Transmission
  762
- Acknowledge
  763
- Clock Synchronization and Arbitration
  765
- Handshaking and Clock Stretching
  766
- Post-Transfer Software Response
  767
- Generation of Repeated START
  768
  - Introduction
    771
  - Modes of Operation
    772
  - Memory Map/Register Definition
    773
Chapter 33

776
- MDHA Control Register (MDCR)
  776
- MDHA Command Register (MDCMR)
  777
- MDHA Status Register (MDSR)
  778
- MDHA Interrupt Status & Mask Registers (MDISR and MDIMR)
  779
- MDHA Data Size Register (MDDSR)
  781
- MDHA Message Data Size Register (MDMDS)
  782
  - Functional Description
    783
  - Initialization/Application Information
    784
  - Performing a Standard HASH Operation with DMA
    785
  - Performing a SHA-1 EHMAC
    787
  - Performing a MAC Operation with the MACFULL Bit
    788
    
    Introduction
    791
    
    Memory Map/Register Definition
    792
Chapter 34

793
- RNG Status Register (RNGSR)
  793
- RNG Entropy Register (RNGER)
  794
  - Functional Description
    795
  - Initialization/Application Information
    796
  - Introduction
    797
  - Memory Map/Register Definition
    801
Chapter 35

802
- SKHA Mode Register (SKMR)
  802
- SKHA Control Register (SKCR)
  803
- SKHA Command Register (SKCMR)
  804
- SKHA Status Register (SKSR)
  805
- SKHA Error Status and Mask Registers (SKESR, SKESMR)
  806
- SKHA Key Size Register (SKKSR)
  808
- SKHA Input FIFO (SKIN)
  809
  - SKHA Context Registers (SKC N )
    810
  - Functional Description
    811
- Transmit FIFO Interface Block
  812
- SKHA Logic Block
  813
- Security Assurance Features
  814
- Initialization/Application Information
  815
- Operation with Context Switch
  816
- Introduction
  817
Chapter 2 Signal Descriptions

818
- Memory Map/Register Definition
  819
- Shared Debug Resources
  820
- Configuration/Status Register (CSR)
  821
- BDM Address Attribute Register (BAAR)
  824
- Address Attribute Trigger Register (AATR)
  825
- Trigger Definition Register (TDR)
  826
- Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR)
  829
- Address Breakpoint Registers (ABLR, ABHR)
  831
- Data Breakpoint and Mask Registers (DBR, DBMR)
  832
  - Functional Description
    833
  - Receive Packet Format
    835
  - Transmit Packet Format
    836
  - Command Sequence Diagrams
    837
  - Bdm Command Set
    839
- Real-Time Debug Support
  854
- Concurrent BDM and Processor Operation
  856
- Debug Translate Block
  859
- Processor Status, Debug Data Definition
  860
- Supervisor Instruction Set
  864
- Freescale-Recommended BDM Pinout
  865
  - Introduction
    867
  - Features
    868
Chapter 37

869
- Test Clock Input (TCLK)
  869
- Test Reset/Development Serial Clock (TRST/DSCLK)
  870
- IDCODE Register
  871
- Boundary Scan Register
  872
- JTAG Instructions
  873

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