Freescale Semiconductor MCF54455 Reference Manual page 283

Universal Serial Bus Interface – On-The-Go Module
See Section 10.3.3.3, "Host Controller Structural Parameters Register (HCSPARAMS)"
information.
10.5.5.1.2 Operational Registers
These additions to the operational registers support the embedded TT:
• Addition of the TTCTRL register.
• Addition of a two-bit port speed (PSPD) field to the PORTSCn register.
10.5.5.1.3 Discovery
In a standard EHCI controller design, the EHCI host controller driver detects a full-speed (FS) or
low-speed (LS) device by noting if the port enable bit is set after the port reset operation. The port enable
is set only in a standard EHCI controller implementation after the port reset operation and when the host
and device negotiate a high-speed connection (chirp completes successfully).
The module always sets the port enable bit after the port reset operation regardless of the result of the host
device chirp result, and the resulting port speed is indicated by the PORTSCn[PSPD] field. Therefore, the
standard EHCI host controller driver requires an alteration to manage directly connected full- and
low-speed devices or hubs. The change is a fundamental one summarized in
Table 10-63. Functional Differences Between EHCI and EHCI with Embedded TT
Standard EHCI
After port enable bit is set following a
connection and reset sequence, the
device/hub is assumed to be HS.
FS and LS devices are assumed to be
downstream from a HS hub.
Therefore, all port-level control
performs through the hub class to the
nearest hub.
FS and LS devices are assumed to be
downstream from a HS hub with
HubAddr equal to X. [where HubAddr
> 0 and HubAddr is the address of the
hub where the bus transitions from HS
to FS/LS (split target hub)]
10.5.5.1.4 Data Structures
The same data structures used for FS/LS transactions though a HS hub are also used for transactions
through the root hub. It is demonstrated here how hub address and endpoint speed fields should be set for
directly attached FS/LS devices and hubs:
1. QH (for direct attach FS/LS) – asynchronous (bulk/control endpoints) periodic (interrupt)
• Hub address equals 0
• Transactions to direct attached device/hub.
10-76
EHCI with embedded Transaction Translator
After port enable bit is set following a connection and
reset sequence, the device/hub speed is noted from
PORTSCn.
FS and LS device can be downstream from a HS hub or
directly attached. When the FS/LS device is downstream
from a HS hub, port-level control acts using the hub class
through the nearest hub. When a FS/LS device is directly
attached, then port-level control is accomplished using
PORTSCn.
FS and LS device can be downstream from a HS hub
with HubAddr equal to X [HubAddr > 0] or directly
attached [where HubAddr equals 0 and HubAddr is the
address of the root hub where the bus transitions from
HS to FS/LS (split target hub is the root hub)]
for usage
Table 10-63.
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