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Field
31–2
Reserved, must be cleared.
1–0
Number of bytes written to transmit FIFO before transmission of a frame begins
TFWR
00 64 bytes written
01 64 bytes written
10 128 bytes written
11 192 bytes written
26.4.20 FIFO Receive Bound Registers (FRBR0 & FRBR1)
FRBRn indicates the upper address bound of the FIFO RAM. Drivers can use this value, along with the
FRSRn, to appropriately divide the available FIFO RAM between the transmit and receive data paths.
Address: 0xFC03_014C (FRBR0)
0xFC03_414C (FRBR1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Field
31–10
Reserved, read as 0 (except bit 10, which is read as 1).
9–2
Read-only. Highest valid FIFO RAM address.
R_BOUND
1–0
Reserved, read as 0.
26.4.21 FIFO Receive Start Registers (FRSR0 & FRSR1)
FRSRn indicates the starting address of the receive FIFO. FRSRn marks the boundary between the
transmit and receive FIFOs. The transmit FIFO uses addresses from the start of the FIFO to the location
four bytes before the address programmed into the FRSRn. The receive FIFO uses addresses from FRSRn
to FRBRn inclusive.
Hardware initializes the FRSRn register at reset. FRSRn only needs to be written to change the default
value.
Freescale Semiconductor
Table 26-23. TFWRn Field Descriptions
Figure 26-20. FIFO Receive Bound Register (FRBRn)
Table 26-24. FRBRn Field Descriptions
Fast Ethernet Controllers (FEC0 and FEC1)
Description
Description
Access: User read-only
8
7
6
5
4
3
2
1
0
R_BOUND
0
0
0
26-26
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