Freescale Semiconductor MCF54455 Reference Manual page 252

Field
1 Reserved, must be cleared.
0 RX endpoint stall. Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the host.
RXS It continues returning STALL until software clears the bit or it automatically clears upon receipt of a new SETUP
request.
0 Endpoint OK
1 Endpoint stalled
10.3.4.23 Endpoint Control Register n (EPCRn)
These registers are not defined in the EHCI specification. There is an EPCRn register for each endpoint in
a device.
Address: 0xFC0B_01C4 (EPCR1)
0xFC0B_01C8 (EPCR2)
0xFC0B_01CA (EPCR3)
31 30 29
R 0 0 0
W
Reset 0 0 0
15 14 13
R 0 0 0
W
Reset 0 0 0
Field
31–24 Reserved, must be cleared.
23 TX endpoint enable.
TXE 0 Disabled
1 Enabled
22 TX data toggle reset. When a configuration event is received for this Endpoint, software must write a 1 to this bit
TXR to synchronize the data PID's between the host and device. This bit is self-clearing.
21 TX data toggle inhibit. This bit is used only for test and should always be written as 0. Writing a 1 to this bit causes
TXI this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet.
0 PID sequencing enabled.
1 PID sequencing disabled.
20 Reserved, must be cleared.
Freescale Semiconductor
Table 10-41. EPCR0 Field Descriptions (continued)
28 27 26 25
0 0 0 0
0 0 0 0
12 11 10 9
0 0 0 0
0 0 0 0
Figure 10-39. Endpoint Control Registers (EPCRn)
Table 10-42. EPCRn Field Descriptions
Universal Serial Bus Interface – On-The-Go Module
Description
24 23 22 21
0 0
TXE TXI
TXR
0 0 0 0
8 7 6 5
0 0
RXE RXI
RXR
0 0 0 0
Description
Access: User read/write
20 19 18 17
0
TXT TXD TXS
0 0 0 0
4 3 2 1
0
RXT RXD RXS
0 0 0 0
10-45
16
0
0
0