Xbs Control Registers (Xbs_Crsn) - Freescale Semiconductor MCF54455 Reference Manual

Field
31 Reserved, must be cleared.
30–28 Master 7 (Serial Boot) priority. Sets the arbitration priority for this port on the associated slave port.
M7 000 This master has level 1 (highest) priority when accessing the slave port.
001 This master has level 2 priority when accessing the slave port.
010 This master has level 3 priority when accessing the slave port.
011 This master has level 4 priority when accessing the slave port.
100 This master has level 5 priority when accessing the slave port.
101 This master has level 6 priority when accessing the slave port.
110 This master has level 7 (lowest) priority when accessing the slave port.
Else Reserved
27 Reserved, must be cleared.
26–24 Master 6 (USB OTG) priority. See M7 description.
M6
23 Reserved, must be cleared.
22–20 Master 5 (PCI controller) priority. See M7 description.
M5
19–15 Reserved, must be cleared.
14–12 Master 3 (FEC1) priority. See M7 description.
M3
11 Reserved, must be cleared.
10–8 Master 2 (FEC0) priority. See M7 description.
M2
7 Reserved, must be cleared.
6–4 Master 1 (eDMA) priority. See M7 description.
M1
3 Reserved, must be cleared.
2–0 Master 0 (ColdFire core) priority. See M7 description.
M0
The possible values for the XBS_PRSn fields depend on the number of
masters available on the device. Because the device contains seven masters,
valid values are 000 to 110. Unpredictable results occur when using the
reserved setting 111.
15.4.2

XBS Control Registers (XBS_CRSn)

The XBS control registers (XBS_CRSn) control several features of each slave port and must be accessed
using 32-bit accesses. After XBS_CRSn[RO] is set, the XBS_CRSn can only be read; attempts to write to
it have no effect and result in an error response.
Freescale Semiconductor
Table 15-3. XBS_PRSn Field Descriptions
Description
NOTE
Crossbar Switch (XBS)
15-5