Freescale Semiconductor MCF54455 Reference Manual page 536

Address: 0xFC0A_8070 (PCIIW0BTAR)
0xFC0A_8074 (PCIIW1BTAR)
0xFC0A_8078 (PCIIW2BTAR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
WBA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–24 Window n base address. One of three base address fields to determine an internal bus hit on PCI. At most,
WBA the upper byte of the address is decoded. The WAM bit field determines what bits of this register to compare
the internal bus address against to generate the hit.
The smallest possible window is a 16-Mbyte block.
23–16 Window n address mask. Masks the corresponding internal bus base address bit of the base address for
WAM Window n (WBA) to instruct the address decode logic to ignore the bit. If the base address mask bit is set, the
associated base address bit of window n is ignored when generating the PCI hit. Bit 16 masks bit 24, bit 17
masks bit 25, and so on.
0 Corresponding address bit used in address decode.
1 Corresponding address bit ignored in address decode.
For internal bus accesses to the window n address range, this byte also determines which upper 8 bits of the
internal bus address to pass on for presentation as a PCI address. Any address bit used to decode the internal
bus address, indicated by a 0 translated. This provides a way to overlay a PCI page address onto the internal
bus address. A 1 in the WAM byte indicates that the internal bus address bit is passed to PCI unaltered.
15–8 Window n translation address. For any translated bit (described above), the corresponding value here is driven
WTA onto the PCI address bus for the internal bus window 0 address hit.
The window translation operation can not be turned off. If a direct mapping from internal bus to PCI space is
desired, program the same value to the window base address register and window translation address
register.
7–0 Reserved, must be cleared.
22.3.2.6 Initiator Window Configuration Register (PCIIWCR)
Address: 0xFC0A_8080 (PCIIWCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Freescale Semiconductor
WAM
Figure 22-19. PCIIWnBTAR Register
Table 22-15. PCIIWnBTAR Field Descriptions
0 0 0 0
W0C W1C
Figure 22-20. PCIIWCR Register
9
WTA
Description
9
0 0 0 0
W2C
PCI Bus Controller
Access: User read/write
8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
Access: User read/write
8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
22-19