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Fast Ethernet Controllers (FEC0 and FEC1)
The 7-wire serial mode interface (RCRn[MII_MODE] cleared and RCR [RMII_MODE] cleared or set)
is generally referred to as AMD mode.
transceiver.
26.5.7
FEC Frame Transmission
The Ethernet transmitter is designed to work with almost no intervention from software. After
ECRn[ETHER_EN] is set and data appears in the transmit FIFO, the Ethernet MAC can transmit onto the
network. The Ethernet controller transmits bytes least significant bit (lsb) first.
When the transmit FIFO fills to the watermark (defined by TFWRn), MAC transmit logic asserts
FECn_TXEN and starts transmitting the preamble (PA) sequence, the start frame delimiter (SFD), and
then the frame information from the FIFO. However, the controller defers the transmission if the network
is busy (FECn_CRS is asserted). Before transmitting, the controller waits for carrier sense to become
inactive, then determines if carrier sense stays inactive for 60 bit times. If so, transmission begins after
waiting an additional 36 bit times (96 bit times after carrier sense originally became inactive). See
Section 26.5.17.1, "Transmission Errors,"
26-37
Table 26-36. RMII Mode Configuration
Signal Description
Reference Clock
Transmit Enable
Transmit Data
Receive Data Valid
Receive Data
Receive Error
Table 26-37
shows the 7-wire mode connections to the external
Table 26-37. 7-Wire Mode Configuration
Signal description
Transmit Clock
Transmit Enable
Transmit Data
Collision
Receive Clock
Receive Data Valid
Receive Data
for more details.
EMAC Pin
FECn_TXCLK
FECn_TXEN
FECn_TXD[1:0]
FECn_RXDV
FECn_RXD[1:0]
FECn_RXER
n
EMAC Pin
FECn_TXCLK
FECn_TXEN
FECn_TXD[0]
FECn_COL
FECn_RXCLK
FECn_RXDV
FECn_RXD[0]
Freescale Semiconductor
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