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Table 21-1. SDRAM Interface—Detailed Signal Descriptions (continued)
Signal
I/O
SD_DQS[3:2]
I/O Data strobes that indicate valid read/write data. (Edge-aligned with read data, centered with write data.)
The DQS frequency equals the memory clock frequency. Data is normally 1/4 memory clock period after a
DQS transition. For DDR operation, there is data following each DQS edge (rising and falling); for SDR
operation, valid data follows the rising edges only. The address correspondence:
SD_DQS3 - SD_D[31:24]
SD_DQS2 - SD_D[23:16]
Note: If a read is attempted from a DDR SDRAM chip select when there is no memory to respond with the
State
Meaning
Timing
SD_WE
O Command input. Along with SD_CS, SD_CAS, and SD_RAS defines the current command.
State
Meaning
Timing
SD_VREF
I
SDRAM reference voltage. Reference voltage for differential I/O pad cells. Should be half the voltage of the
memory used in the system. For example, 2.5V DDR results in an SD_VREF of 1.25V. See the device's
datasheet for the voltages and tolerances for the various memory modes.
21.3
Interface Recommendations
21.3.1
Supported Memory Configurations
The SDRAM controller supports up to 14 row addresses and up to 13 column addresses. However, the
maximum row and column addresses are not simultaneously supported. The number of row and column
addresses must be less than or equal to 25. In addition to row/column address lines, there are always two
row bank address bits. Therefore, the greatest possible address space accessed using a single chip select is
27
2
x 16 bit or 256 MBytes.
Table 21-3
and
Table 21-4
configurations. When the SDRAM controller receives the internal module enable, it latches the internal
bus address lines IA[27:0] (IA equals internal address) and multiplexes them into row, column, and bank
addresses (RA, CA, and BA respectfully). IA[9:1] are used for CA[8:0]. IA[11:10] are used for BA[1:0],
and IA[23:12] are used for RA[11:0]. IA[27:24] can be used for additional row or column address bits, as
needed. The additional row- or column-address bits are programmed via the SDCR[ADDR_MUX] bits.
Freescale Semiconductor
appropriate SD_DQS pulses, the bus cycle hangs. Because there is no high level bus monitor on the
device, a reset is the only way to exit this error condition.
Asserted — Similar to a clock signal, the edges are more important than being asserted or
negated.
High impedance — Depending on the SDCFG1[OE_RULE] bit, the SD_DQS can be in high
impedance until a write is occurring or only when a read is occurring.
Assertion/Negation — Occurs on crossing of SD_CLK and SD_CLK.
Please see
Table 21-10
for SDRAM commands.
Assertion/Negation— Occurs synchronously with SD_CLK.
show the address multiplexing used by the memory controller for different
Description
SDRAM Controller (SDRAMC)
21-5
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