Freescale Semiconductor MCF54455 Reference Manual page 151

Cache
Field
29 Enable data store buffer. Affects the precision of transfers.
DESB 0 Imprecise-mode, write-through or cache-inhibited writes bypass the store buffer and generate bus cycles
directly. Section 6.4.4.2.1, "Push and Store
1 The four-entry FIFO store buffer is enabled; to maximize performance, this buffer defers pending
imprecise-mode, write-through or cache-inhibited writes.
Precise-mode, cache-inhibited accesses always bypass the store buffer. Precise and imprecise modes are
described in Section 6.4.1.2, "Cache-Inhibited
28 Data disable CPUSHL invalidate.
DDPI 0 Normal operation. A CPUSHL instruction causes the selected line to be pushed if modified, then invalidated.
1 No clear operation. A CPUSHL instruction causes the selected line to be pushed if modified, then left valid.
27 Data cache half-data lock.
DHLCK 0 Normal operation. The cache allocates the lowest invalid way. If all ways are valid, the cache allocates the way
pointed at by the round-robin counter and then increments this counter.
1 Half-cache operation. The cache allocates to the lower invalid way of levels 2 and 3; if both are valid, the cache
allocates to Way 2 if the high-order bit of the round-robin counter is zero; otherwise, it allocates Way 3 and
increments the round-robin counter. This locks the contents of ways 0 and 1. Ways 0 and 1 are still updated
on write hits and may be pushed or cleared by specific cache push/invalidate instructions.
26–25 Default data-cache mode. For normal operations that do not hit in the RAMBARs or ACRs, this field defines the
DDCM effective cache mode.
00 Cacheable write-through imprecise
01 Cacheable copyback
10 Cache-inhibited precise
11 Cache-inhibited imprecise
Precise and imprecise accesses are described in
24 Data cache invalidate all. Setting this bit initiates entire cache invalidation. After invalidation is complete, this bit
DCINVA automatically clears; it is not necessary to clear it explicitly. The caches are not cleared on power-up or normal
reset, as shown in
0 No invalidation is performed.
1 Initiate invalidation of the entire data cache. The cache controller sequentially clears V and M bits in all sets.
Subsequent data accesses stall until the invalidation is finished, at which point, this bit is automatically
cleared. In copyback mode, the cache should be flushed using a CPUSHL instruction before setting this bit.
23 Data default supervisor-protect. For normal operations that do not hit in the RAMBAR or ACRs, this field defines
DDSP supervisor-protection
0 Not supervisor protected
1 Supervisor protected. User operations cause a fault
22–21 Reserved, must be cleared.
20 Invalidate only. Setting this bit forces the invalidation of only the referenced cache line when a CPUSHL
IVO instruction executes. See
19 Enable branch cache.
BEC 0 Branch cache disabled. This may be useful if code is unlikely to be reused.
1 Branch cache enabled.
18 Branch cache invalidate all. Invalidation occurs when this bit is set. Branch caches are not cleared on power-up
BCINVA or normal reset.
0 No invalidation is performed.
1 Initiate an invalidation of the entire branch cache.
17–16 Reserved, must be cleared.
6-6
Table 6-3. CACR Field Descriptions (continued)
Buffers," describes the associated performance penalty.
Accesses."
Figure 6-3.
Section 6.4.8, "CPUSHL Enhancements,"
Description
Section 6.4.1.2, "Cache-Inhibited
for more information.
Accesses."
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