External Signal Description - Freescale Semiconductor MCF54455 Reference Manual

22.2

External Signal Description

A list of the PCI external signals and their properties are discussed below. For detailed description of the
PCI bus signals, see the PCI Local Bus Specification, Revision 2.2.
Name
PCI_AD[31:0]
PCI_CLK
PCI_CBE[3:0]
PCI_DEVSEL
PCI_FRAME
PCI_GNT[3:0]
PCI_IDSEL
PCI_INTA
PCI_IRDY
PCI_PAR
PCI_PERR
PCI_REQ[3:0]
PCI_RST
PCI_SERR
PCI_STOP
PCI_TRDY
1
Arbitration signal function when PCI Arbiter is disabled.
22.2.1 Address/Data Bus (PCI_AD[31:0])
The PCI_AD[31:0] lines are a time multiplexed address/data bus. The address is presented on the bus
during the address phase while the data is presented on the bus during one or more data phases.
22.2.2 Clock (PCI_CLK)
The PCI_CLK signal serves as a reference clock for generation of the internal PCI clock. For more
information, see Section 22.4.6, "PCI Clock Scheme."
22.2.3 Command/Byte Enables (PCI_CBE[3:0])
The PCI_CBE[3:0] signals are time multiplexed. The PCI command is presented during the address phase
and the byte enables are presented during the data phase. Byte enables are active low.
Freescale Semiconductor
Table 22-1. PCI Module External Signals
1
Secondary
— PCI Address Data Bus
—
— PCI Command/Bytes Enables
— PCI Device Select
—
PCI_REQOUT PCI Grants/Request Out
— PCI Initialization Device Select
— PCI Interrupt A
— PCI Initiator Ready
—
— PCI Parity Error
PCI_GNTIN PCI Requests/Grant In
—
— PCI System Error
—
— PCI Target Ready
Function Type
I/O
PCI Clock
I/O
I/O
PCI Frame I/O
O
O
I/O
PCI Parity I/O
I/O
PCI Reset O
I/O
PCI Stop I/O
I/O
PCI Bus Controller
Reset
Tristate
I Toggling
Tristate
Tristate
Tristate
Tristate
I Tristate
0
Tristate
Tristate
Tristate
I Tristate
0
Tristate
Tristate
Tristate
22-3