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17.2.10 Software and Level 1–7 IACK Registers (SWIACKn,
L1IACKn–L7IACKn)
The eight IACK registers (per interrupt controller) can be explicitly addressed via the CPU, or implicitly
addressed via a processor-generated interrupt acknowledge cycle during exception processing. In either
case, the interrupt controller's actions are very similar.
First, consider an IACK cycle to a specific level: a level-n IACK. When this type of IACK arrives in the
interrupt controller, the controller examines all the currently-active level n interrupt requests, determines
the highest priority within the level, and then responds with the unique vector number corresponding to
that specific interrupt source. The vector number is supplied as the data for the byte-sized IACK read cycle.
In addition to providing the vector number, the interrupt controller also loads the level into the CLMASK
register, where it may be retrieved later.
This interrupt controller design also supports the concept of a software IACK. A software IACK allows
an interrupt service routine to determine if there are other pending interrupts so that the overhead
associated with interrupt exception processing (including machine state save/restore functions) can be
minimized. In general, the software IACK is performed near the end of an interrupt service routine, and if
there are additional active interrupt sources, the current interrupt service routine (ISR) passes control to
the appropriate service routine, but without taking another interrupt exception.
When the interrupt controller receives a software IACK read, it returns the vector number associated with
the highest unmasked interrupt source for that interrupt controller. If there are no active sources, the
interrupt controller returns an all-zero vector as the operand for the SWIACK register. A read from the
LnIACK registers when there are no active requests returns a value of 24 (0x18), signaling a spurious
interrupt.
In addition to the software IACK registers in each interrupt controller, there are global software IACK
registers. A read from the global SWIACK (GSWIACK) returns the vector number for the highest level
and priority unmasked interrupt source from all interrupt controllers. A read from one of the global
LnIACK (GLnIACK) registers returns the vector for the highest priority unmasked interrupt within a level
for all interrupt controllers.
Address: 0xFC04_80E0 (SWIACK0)
0xFC04_80E0+4n (LnIACK0) n=1:7
0xFC04_C0E0 (SWIACK1)
0xFC04_C0E0+4n (LnIACK1) n=1:7
0xFC05_40E0 (GSWIACK)
0xFC05_40E0+4n (GLnIACK) n=1:7
7
R
W
Reset
0
(SWIACKn):
Reset
0
(LnIACKn):
Figure 17-13. Software and Level n IACK Registers (SWIACKn, L1IACKn – L7IACKn)
Freescale Semiconductor
6
5
4
VECTOR
0
0
0
0
0
1
Interrupt Controller Modules
Access: User read-only
3
2
1
0
0
0
1
0
0
0
0
0
17-15
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