Interrupt Sources - Freescale Semiconductor MCF54455 Reference Manual

Interrupt Controller Modules
17.2.9.1

Interrupt Sources

Table 17-15 and Table 17-16
INTC1.
Source Module Flag
0
1 EPFR[EPF1]
2 EPFR[EPF2]
3 EPFR[EPF3]
4 EPORT EPFR[EPF4]
5 EPFR[EPF5]
6 EPFR[EPF6]
7 EPFR[EPF7]
8 EDMA_INTR[INT00] DMA Channel 0 transfer complete
9 EDMA_INTR[INT01] DMA Channel 1 transfer complete
10 EDMA_INTR[INT02] DMA Channel 2 transfer complete
11 EDMA_INTR[INT03] DMA Channel 3 transfer complete
12 EDMA_INTR[INT04] DMA Channel 4transfer complete
13 EDMA_INTR[INT05] DMA Channel 5 transfer complete
14 EDMA_INTR[INT06] DMA Channel 6 transfer complete
15 EDMA_INTR[INT07] DMA Channel 7 transfer complete
16 DMA EDMA_INTR[INT08] DMA Channel 8 transfer complete
17 EDMA_INTR[INT09] DMA Channel 9 transfer complete
18 EDMA_INTR[INT10] DMA Channel 10 transfer complete Write EDMA_CINTR[CINT] = 10
19 EDMA_INTR[INT11] DMA Channel 11 transfer complete Write EDMA_CINTR[CINT] = 11
20 EDMA_INTR[INT12] DMA Channel 12 transfer complete Write EDMA_CINTR[CINT] = 12
21 EDMA_INTR[INT13] DMA Channel 13 transfer complete Write EDMA_CINTR[CINT] = 13
22 EDMA_INTR[INT14] DMA Channel 14 transfer complete Write EDMA_CINTR[CINT] = 14
23 EDMA_INTR[INT15] DMA Channel 15 transfer complete Write EDMA_CINTR[CINT] = 15
24 EDMA_ERR[ERRn] DMA Error Interrupt
25 SCM SCMIR[CWIC]
26 UART0 UISR0 register
27 UART1 UISR1 register
28 UART2 UISR2 register
29
17-12
list the interrupt sources for each interrupt request line for INTC0 and
Table 17-15. Interrupt Source Assignment For INTC0
Source Description
Edge port flag 1
Edge port flag 2
Edge port flag 3
Edge port flag 4
Edge port flag 5
Edge port flag 6
Edge port flag 7
Core Watchdog Timeout
UART0 Interrupt Request
UART1 Interrupt Request
UART2 Interrupt Request
Flag Clearing Mechanism
Not Used
Write EPF1 = 1
Write EPF2 = 1
Write EPF3 = 1
Write EPF4 = 1
Write EPF5 = 1
Write EPF6 = 1
Write EPF7 = 1
Write EDMA_CINTR[CINT] = 0
Write EDMA_CINTR[CINT] = 1
Write EDMA_CINTR[CINT] = 2
Write EDMA_CINTR[CINT] = 3
Write EDMA_CINTR[CINT] = 4
Write EDMA_CINTR[CINT] = 5
Write EDMA_CINTR[CINT] = 6
Write EDMA_CINTR[CINT] = 7
Write EDMA_CINTR[CINT] = 8
Write EDMA_CINTR[CINT] = 9
Write EDMA_CERR[CERR] = n
Write SCMISR[CWIC] = 1
Automatically cleared
Automatically cleared
Automatically cleared
Not Used
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