Mmu Implementation; Tlb Address Fields - Freescale Semiconductor MCF54455 Reference Manual

Memory Management Unit (MMU)
JADDR, J Control
J
KC1
To processor local bus
control for TLB miss
Figure 4-11. Processor Local Bus Address and Attributes Generation
4.3.8

MMU Implementation

The MMU implements a 64-entry full-associative Harvard TLB architecture with 32-entry ITLB and
DTLB. This section details the operation and looks at the size, frequency, miss rate, and miss recovery time
of this TLB implementation.
4.3.8.1

TLB Address Fields

Because the TLB has a total of 64 entries (32 each for the instruction and data TLBs), a 6-bit address field
is necessary. TLB addresses 0–31 reference the ITLB; TLB addresses 32–63 reference the DTLB.
In the MMUOR register, bits 0–5 of the TLB allocation address (AA[5–0]) have this address format. The
remaining TLB allocation address bits (AA[15–6]) are ignored on updates and always read as zero.
When the MMUAR register is used for a TLB address, bits FA[5–0] also have this address format. The
remaining form address bits (FA[31–6]) are ignored when this register is used for a TLB address.
4-20
To processor local bus memory controllers
TLB tag TLB data
entries
entries
Comp
TLB hit
entry
data
Translated address
TLB Hit
MMU's access control
logic
KC1 cycle address control
Memory unit access control
(MMUBAR, RAMBAR, ACRs, CACR
priority hit logic)
To processor local bus
control for TLB miss
logic
Untranslated address
mapping register's
access control
Mapping register hit
or special mode access
To processor local bus
memory controllers plus
internal-to-external memory
bus interface
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