Memory Map/Register Definition - Freescale Semiconductor MCF54455 Reference Manual

Entering limp mode via the MISCCR[LIMP] bit requires a special procedure for the SDRAM module. As
noted above, the SDRAM controller is disabled in limp mode, so follow these two critical steps before
setting the MISCCR[LIMP] bit:
1. Code execution must be transferred to another memory resource. Primary options are whatever
memory device is attached to the FlexBus boot chip-select or on-chip SRAM (but not the CPU
cache, as it may have to be flushed upon limp mode entrance or exit).
2. The SDRAM controller must be placed in self-refresh mode to avoid data loss while the SDRAMC
shuts down.
8.1.3.4 Low-power Mode Operation
This subsection describes the clock module operation in low-power and halted modes of operation.
Low-power modes are described in
operation in low-power modes.
Low-power Mode
Wait
Doze
Stop
Halted
In wait and doze modes, the system clocks to the peripherals are enabled, and the clocks to the core, and
SRAM are stopped. Each module can disable its clock locally at the module level.
In stop mode, all system clocks are disabled (except the real-time clock that continues to run via its external
clock). There are several options for enabling or disabling the PLL or crystal oscillator in stop mode,
compromising between stop mode current and wake-up recovery time. The PLL can be disabled in stop
mode, but requires a wake-up period before it relocks. The oscillator can also be disabled during stop
mode, but it requires a wake-up period to restart.
When the PLL is enabled in stop mode (LPCR[STPMD] = 00), the external FB_CLK signal can support
systems using FB_CLK as the clock source. For more information about operating the PLL in stop mode,
see Section 9.2.5, "Low-Power Control Register (LPCR)."
There is also a fast wake-up option for quickly enabling the system clocks during stop recovery
(LPCR[FWKUP]). This eliminates the wake-up recovery time but at the risk of sending a potentially
unstable clock to the system.
8.2

Memory Map/Register Definition

The PLL programming model consists of the following:
Freescale Semiconductor
Chapter 9, "Power Management." Table 8-1
Table 8-1. Clock Module Operation in Low-power Modes
Clock Operation
Clocks sent to peripheral modules only
Clocks sent to peripheral modules only
All system clocks disabled
Normal
shows the clock module
Mode Exit
Clock module does not cause exit, but normal
clocking resumes upon mode exit
Clock module does not cause exit, but normal
clocking resumes upon mode exit
Clock module does not cause exit, but clock
sources are re-enabled and normal clocking
resumes upon mode exit
Clock module does not cause exit
Clock Module
8-5