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16.3.7
PCI Mode Select Control Register (MSCR_PCI)
The MSCR_PCI register controls the slew rate mode of the following PCI pins: PCI_AD[31:0],
PCI_CBE[3:0], PCI_DEVSEL, PCI_FRAME, PCI_GNT[3:0], PCI_IDSEL, PCI_IRDY, PCI_PAR,
PCI_PERR, PCI_REQ[3:0], PCI_RST, PCI_SERR, PCI_STOP, PCI_TRDY, and IRQ1.
Address: 0xFC0A_4075 (MSCR_PCI)
7
R
0
W
Reset:
0
Note: Reset state is 1 when BOOTMOD[1:0] equals 00, the value of FB_AD[2] when BOOTMOD[1:0]
equals 10, or the value of serial boot bit 104 when BOOTMOD[1:0] equals 11.
Figure 16-49. PCI Mode Select Control Register (MSCR_PCI)
Field
7–1
Reserved, should be cleared.
0
PCI slew rate mode bit. Sets the slew rate mode for the PCI pins.
MSCR_PCI
0 Low slew rate mote (33 MHz)
1 High slew rate mode (66 MHz)
16.3.8
Drive Strength Control Registers (DSCR_x)
The drive strength control registers set the output pin drive strengths. All drive strength control registers
are read/write.
These drive strength settings are effective in all non-JTAG modes,
regardless of the current functions of the pins.
Freescale Semiconductor
6
5
4
0
0
0
0
0
0
Table 16-24. MSCR_PCI Field Descriptions
Description
NOTE
Pin Multiplexing and Control
Access: User read/write
3
2
1
0
0
0
0
0
0
0
MSCR_PCI
See Note
16-39
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