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ColdFire Core
All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers.
This allows any handler to disable interrupts effectively, if necessary, by raising the interrupt mask level
contained in the status register. For more details, see ColdFire Family Programmer's Reference Manual.
3.3.3.1
Exception Stack Frame Definition
Figure 3-10
shows exception stack frame. The first longword contains the 16-bit format/vector word (F/V)
and the 16-bit status register, and the second longword contains the 32-bit program counter address.
31 30 29 28 27
SSP
Format
FS[3:2]
+ 0x4
The 16-bit format/vector word contains three unique fields:
•
A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by
the processor, indicating a two-longword frame format. See
Original SSP @ Time
of Exception, Bits 1:0
•
There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for
access and address errors only and written as zeros for all other exceptions. See
FS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
3-17
26 25 24 23 22 21 20 19 18 17
Vector
Program Counter
Figure 3-10. Exception Stack Frame Form
Table 3-6. Format Field Encodings
SSP @ 1st
Instruction of
Handler
00
Original SSP - 8
01
Original SSP - 9
10
Original SSP - 10
11
Original SSP - 11
Table 3-7. Fault Status Encodings
Not an access or address error nor an interrupted debug service routine
Interrupt during a debug service routine for faults other than access errors
Error on instruction fetch
TLB miss on opword of instruction fetch
TLB miss on extension word of instruction fetch
IFP access error while executing in emulator mode
Error on operand write
Attempted write to write-protected space
16 15 14 13 12 11 10 9
FS[1:0]
Status Register
Table
3-6.
Format Field
0100
0101
0110
0111
Definition
Reserved
Reserved
8
7
6
5
4
3
2
1
0
Table
3-7.
1
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