Tlb Locked Entries - Freescale Semiconductor MCF54455 Reference Manual

Memory Management Unit (MMU)
Binary state bits are updated on all TLB write (load) operations, as well as normal non-locked entries ITLB
and DTLB hits. Also, if all entries in a binary state are locked, then that state is always set. That is, if entries
15, 14, 13, and 12 were locked, LRU state bit rdRecent15To14 is forced to 1.
For a completely valid TLB, binary state information determines the LRU entry. The replacement
algorithm is deterministic and, for the case of a full TLB (with no locked entries and always touching new
pages), the replacement entry repeats every 32 TLB loads.
4.3.8.3

TLB Locked Entries

Figure 4-12 is a ColdFire MMU Harvard TLB block diagram.
For TLB miss faults, the instruction restart model re-executes an instruction on returning from the
exception handler. An instruction can touch two instruction pages (a 32- or 48-bit instruction can straddle
two pages) or four data pages (a memory-to-memory word or longword move where misaligned source
and destination operands straddle two pages). Therefore, one instruction may take two ITLB misses and
allocate two ITLB pages before completion. Likewise, one instruction may require four DTLB misses and
allocate four DTLB pages. Because of this, a pool of unlocked TLB entries must be available if virtual
memory is used.
The above examples show the fewest entries needed to guarantee an instruction can complete execution.
For good MMU performance, more unlocked TLB entries should be available.
4-22
Table 4-14. PLRU State Bits (continued)
State Bits
rdRecent25 A 1 indicates 25 is more recent than 24
rdRecent23 A 1 indicates 23 is more recent than 22
rdRecent21 A 1 indicates 21 is more recent than 20
rdRecent19 A 1 indicates 19 is more recent than 18
rdRecent17 A 1 indicates 17 is more recent than 16
rdRecent15 A 1 indicates 15 is more recent than 14
rdRecent13 A 1 indicates 13 is more recent than 12
rdRecent11 A 1 indicates 11 is more recent than 10
rdRecent09 A 1 indicates 09 is more recent than 08
rdRecent07 A 1 indicates 07 is more recent than 06
rdRecent05 A 1 indicates 05 is more recent than 04
rdRecent03 A 1 indicates 03 is more recent than 02
rdRecent01 A 1 indicates 01 is more recent than 00
Meaning
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