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Random Number Generator (RNG)
Field
2
Interrupt mask.
IM
0 Error interrupt enabled.
1 Error interrupt masked.
1
High assurance. Notifies core when FIFO underflow has occurred (FIFO is read while empty). Enables the security
HA
violation bit in the RNGSR. Bit is sticky and only cleared by hardware reset.
0 Disable security violation notification.
1 Enable security violation notification.
0
Go bit. Starts/stops random data from being generated. Bit is sticky and only cleared by hardware reset.
GO
0 FIFO not loaded with random data.
1 FIFO loaded with random data.
25.2.2
RNG Status Register (RNGSR)
The RNGSR, shown in
Figure
: 0xFC0B_4004 (RNGSR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.
Field
31–24
Reserved, must be cleared.
23–16
Output FIFO size. Indicates size of the output FIFO (16 words) and maximum possible value of RNGR[OFL].
OFS
15–8
Output FIFO level. Indicates current number of random words in the output FIFO. Determines if valid random data
OFL
is available for reading from the FIFO without causing an underflow condition.
7–5
Reserved, must be cleared.
4
Sleep. This bit reflects whether the RNG is in sleep mode. When this bit is set, the RNGA is in sleep mode and the
SLP
oscillator clocks are inactive. While in this mode, the FIFO is not loaded and the FIFO level does not increase.
0 RNGA is not in sleep mode.
1 RNGA is in sleep mode.
3
Error interrupt. Signals a FIFO underflow. Reset by a write to RNGCR[CI] and not masked by RNGCR[IM].
EI
0 FIFO not read while empty.
1 FIFO read while empty.
2
FIFO underflow. Signals FIFO underflow. Reset by reading RNGSR.
FUF
0 FIFO not read while empty since last read of RNGSR.
1 FIFO read while empty since last read of RNGSR.
25-3
Table 25-2. RNGCR Field Descriptions (continued)
Description
25-2, is a read only register which reflects the internal status of the RNG.
OFS
Figure 25-2. RNG Status Register (RNGSR)
Table 25-3. RNGSR Field Descriptions
Description
9
8
7
6
5
4
OFL
0 0 0 SLP EI FUF LRS SV
0
Freescale Semiconductor
Access: User read-only
3
2
1
0
0
0
0
0
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