Freescale Semiconductor ColdFire MCF52210 ColdFire MCF52211 ColdFire MCF52212 ColdFire MCF52213 Manuals

Manuals and User Guides for Freescale Semiconductor ColdFire MCF52210 ColdFire MCF52211 ColdFire MCF52212 ColdFire MCF52213. We have 1 Freescale Semiconductor ColdFire MCF52210 ColdFire MCF52211 ColdFire MCF52212 ColdFire MCF52213 manual available for free PDF download: Reference Manual

Freescale Semiconductor ColdFire MCF52210 ColdFire MCF52211 ColdFire MCF52212 ColdFire MCF52213 Reference Manual (576 pages)

ColdFire Integrated Microcontroller

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 6 MB

Signal Descriptions

3
- Table of Contents
  3
- Chapter 1 Overview
  
  17
  - MCF52211 Coldfire® Integrated Microcontroller Reference Manual
    17
  - MCF52211 Family Configurations
    18
    
    Block Diagram
    19
  - Part Numbers and Packaging
    19
    
    Features
    20
    
    Integrated Debug Module
    24
    
    V2 Core Overview
    24
    
    Jtag
    25
    
    Flash Memory
    26
    
    On-Chip Memories
    26
    
    Power Management
    26
    
    USB On-The-Go Controller
    26
    
    DMA Timers (DTIM0–DTIM3)
    27
    
    Fast ADC
    27
    
    Qspi
    27
    
    Uarts
    27
    
    General Purpose Timer (GPT)
    28
    
    Periodic Interrupt Timers (PIT0 and PIT1)
    28
    
    Pulse-Width Modulation (PWM) Timers
    28
    
    Real-Time Clock (RTC)
    28
    
    Software Watchdog Timer
    28
    
    Interrupt Controller (INTC)
    29
    
    Phase-Locked Loop (PLL)
    29
    
    Reset
    29
- Chapter 7 Backup Watchdog Timer
  
  29
  - DMA Controller
    29
  - Gpio
    30
- Chapter 2 Signal Descriptions
  
  31
  - Introduction
    31
  - Overview
    31
  - Pin Functions
    32
  - Mode Selection
    38
  - PLL and Clock Signals
    38
  - Reset Signals
    38
  - External Interrupt Signals
    39
    
    Queued Serial Peripheral Interface (QSPI)
    39
  - DMA Timer Signals
    40
  - UART Module Signals
    40
  - ADC Signals
    41
  - Debug Support Signals
    41
  - General Purpose Timer Signals
    41
  - Pulse-Width Modulator Signals
    41
  - Ezport Signal Descriptions
    43
  - Power and Ground Pins
    43
    
    Introduction
    45
    
    Overview
    45
- Chapter 3 Coldfire Core
  
  45
  - Memory Map/Register Description
    46
  - Address Registers (A0–A6)
    48
  - Data Registers (D0–D7)
    48
  - Supervisor/User Stack Pointers (A7 and OTHER_A7)
    48
  - Condition Code Register (CCR)
    49
  - Program Counter (PC)
    50
  - Vector Base Register (VBR)
    50
  - Status Register (SR)
    51
  - Functional Description
    52
  - Memory Base Address Registers (RAMBAR, FLASHBAR)
    52
  - Version 2 Coldfire Microarchitecture
    52
  - Instruction Set Architecture (ISA_A+)
    57
  - Exception Processing Overview
    58
  - Exception Stack Frame Definition
    60
  - Processor Exceptions
    61
    
    Address Error Exception
    62
    
    Illegal Instruction Exception
    62
    
    Divide-By-Zero
    63
    
    Privilege Violation
    63
    
    Trace Exception
    63
    
    Debug Interrupt
    64
    
    Rte and Format Error Exception
    64
    
    Interrupt Exception
    65
    
    Reset Exception
    65
    
    Trap Instruction Exception
    65
  - Instruction Execution Timing
    69
    
    Timing Assumptions
    69
    
    Move Instruction Execution Times
    70
    
    Standard One Operand Instruction Execution Times
    71
    
    Standard Two Operand Instruction Execution Times
    72
    
    Miscellaneous Instruction Execution Times
    73
    
    Mac Instruction Execution Times
    74
    
    Branch Instruction Execution Times
    75
    
    Introduction
    77
    
    Overview
    77
- Chapter 4
  
  78
  - MAC Status Register (MACSR)
    78
  - Memory Map/Register Definition
    78
  - Mask Register (MASK)
    80
  - Accumulator Register (ACC)
    81
  - Functional Description
    82
  - Fractional Operation Mode
    83
  - MAC Instruction Set Summary
    84
  - Data Representation
    85
  - MAC Instruction Execution Times
    85
  - MAC Opcodes
    85
  - Features
    91
  - Introduction
    91
  - Memory Map/Register Description
    91
- Chapter 5 Static RAM (SRAM)
  
  91
  - Overview
    91
  - Register Descriptions
    91
  - SRAM Base Address Register (RAMBAR)
    92
    
    Initialization/Application Information
    93
    
    Power Management
    94
  - SRAM Initialization Code
    94
- Chapter 21
  
  95
  - Features
    95
    
    Backup Watchdog Timer Mode
    95
- Chapter 6 Clock Module
  
  95
  - Introduction
    95
  - Modes of Operation
    95
  - External Clock Mode
    96
  - Low-Power Mode Operation
    96
  - Normal PLL Mode
    96
  - RTC Mode
    96
  - Block Diagram
    97
  - Clkmod[1:0]
    99
  - Clkout
    99
  - Extal
    99
    
    Signal Descriptions
    99
    
    Memory Map and Registers
    100
    
    Register Descriptions
    100
    
    Rsto
    100
    
    Synthesizer Control Register (Syncr)
    101
    
    Relaxation Oscillator Control Register (Rocr)
    105
    
    Clock Control High Register (Cchr)
    106
    
    Clock Control Low Register (Cclr)
    106
    
    Oscillator Control High Register (Ochr)
    107
    
    Oscillator Control Low Register (Oclr)
    108
    
    Backup Watchdog Timer Control Register (Bwcr)
    110
  - Clock Operation During Reset
    111
  - Functional Description
    111
  - System Clock Modes
    111
  - PLL Operation
    112
  - System Clock Generation
    112
  - Modes of Operation
    123
  - Memory Map and Register Definition
    124
    
    Functional Description
    128
    
    Features
    129
    
    Introduction
    129
    
    Memory Map/Register Definition
    129
- Chapter 8 Power Management
  
  129
  - Peripheral Power Management Registers (PPMRH, PPMRL)
    130
  - Peripheral Power Management Register Low (Ppmrl)
    132
  - Low-Power Interrupt Control Register (Lpicr)
    133
  - Peripheral Power Management Set Register (Ppmrs)
    135
  - Low-Power Control Register (Lpcr)
    136
  - Peripheral Power Management Clear Register (Ppmrc)
    136
  - IPS Bus Timeout Monitor
    137
    
    Functional Description
    138
    
    Low-Power Modes
    138
    
    Doze Mode
    139
    
    Peripheral Shut down
    139
    
    Run Mode
    139
    
    Stop Mode
    139
    
    Wait Mode
    139
    
    Peripheral Behavior in Low-Power Modes
    140
    
    Clock Module
    142
    
    Reset Controller
    142
    
    Summary of Peripheral State During Low-Power Modes
    143
  - External Signal Descriptions
    145
  - Introduction
    145
    
    Features
    145
- Chapter 9 Chip Configuration Module (CCM)
  
  145
  - Clkmod[1:0]
    146
  - Jtag_En
    146
  - Memory Map/Register Definition
    146
  - Programming Model
    146
  - Rcon
    146
  - Test
    146
    
    Chip Configuration Register (CCR)
    147
    
    Memory Map
    147
    
    Register Descriptions
    147
    
    Chip Identification Register (CIR)
    148
    
    Reset Configuration Register (RCON)
    148
  - Block Diagram
    151
- Chapter 10 Reset Controller Module
  
  151
  - Features
    151
  - Introduction
    151
  - Memory Map and Registers
    152
    
    Reset Control Register (RCR)
    153
    
    Reset Status Register (RSR)
    154
    
    Functional Description
    155
    
    Reset Sources
    155
    
    Software Reset
    156
    
    Reset Control Flow
    157
    
    Concurrent Resets
    159
    
    Introduction
    161
  - Signals
    152
    
    Rsti
    152
    
    Rsto
    152
  - Overview
    161
    
    Features
    161
- Chapter 11 Real-Time Clock
  
  161
  - Memory Map/Register Definition
    162
  - Modes of Operation
    162
    
    Register Descriptions
    162
    
    RTC Control Register (RTCCTL)
    167
    
    RTC Interrupt Status Register (RTCISR)
    168
    
    Functional Description
    173
  - Prescaler and Counter
    173
  - Alarm
    174
  - Flow Chart of RTC Operation
    174
  - Initialization/Application Information
    174
  - Minute Stopwatch
    174
  - Code Example for Initializing the Real-Time Clock
    175
- Chapter 12 System Control Module (SCM)
  
  177
  - Features
    177
  - Introduction
    177
  - Overview
    177
  - Memory Map and Register Definition
    178
  - Internal Peripheral System Base Address Register (IPSBAR)
    179
  - Register Descriptions
    179
  - Memory Base Address Register (RAMBAR)
    180
  - Core Reset Status Register (Crsr)
    182
  - Core Watchdog Control Register (Cwcr)
    183
  - Core Watchdog Service Register (Cwsr)
    184
  - Internal Bus Arbitration
    185
    
    Arbitration Algorithms
    186
    
    Bus Master Park Register (MPARK)
    186
    
    Features
    188
    
    Overview
    188
  - Overview
    185
  - System Access Control Unit (SACU)
    188
    
    Memory Map/Register Definition
    189
    
    Master Privilege Register (MPR)
    190
    
    Introduction
    195
- Chapter 13 General Purpose I/O Module
  
  195
  - Features
    196
  - Memory Map/Register Definition
    196
  - Overview
    196
  - Ports Memory Map
    196
  - Signal Descriptions
    196
  - Port Output Data Registers (Portn)
    198
  - Register Descriptions
    198
  - Port Data Direction Registers (Ddrn)
    199
  - Port Pin Data/Set Data Registers (Portnp/Setn)
    201
  - Port Clear Output Data Registers (Clrn)
    203
  - Pin Assignment Registers
    204
  - Pad Control Registers
    207
  - Ports Interrupts
    209
  - K/Coldfire Interrupt Architecture Overview
    211
- Chapter 14 Interrupt Controller Theory of Operation
  
  212
  - Interrupt Prioritization
    213
  - Memory Map
    214
  - Register Descriptions
    215
    
    Interrupt Pending Registers (Iprhn, Iprln)
    216
    
    Interrupt Mask Register (Imrhn, Imrln)
    217
    
    Interrupt Force Registers (Intfrchn, Intfrcln)
    218
    
    Interrupt Acknowledge Level and Priority Register (Iacklprn)
    220
    
    Interrupt Request Level Register (Irlrn)
    220
    
    Interrupt Control Registers (Icrnx)
    221
    
    Interrupt Sources
    223
    
    Software and Level M IACK Registers (Swiackn, Lmiackn)
    225
    
    Global Level M IACK Registers (Glmiack)
    226
  - Low-Power Wakeup Operation
    226
    
    Introduction
    229
- Chapter 15
  
  231
  - USB On-The-Go
    231
  - Buffer Descriptor Table
    232
  - Functional Description
    232
  - Programmers Interface
    232
    
    Data Structures
    232
    
    USB-FS Features
    232
    
    Addressing Buffer Descriptor Table Entries
    233
    
    Rx Vs. Tx as a USB Target Device or USB Host
    233
    
    Buffer Descriptor Formats
    234
    
    USB Transaction
    236
  - Memory Map/Register Definitions
    237
    
    Capability Registers
    238
15.4.1.5 Otg Interrupt Status Register (Otg_Int_Stat)

241
- Ipsbar
  242
  - Field
    242
  - Reset
    242
- Line_Stat
  242
  - Reserved
    242
- OTG Interrupt Status Register (OTG_INT_STAT)
  242
  - 1_Msec Line_State
    242
  - Access: User Read/Write
    243
  - Reserved A_VBUS
    243
  - Sess_Vld B_Sess
    243
  - Status Register (STAT)
    249
- Sess_Vld
  242
  - A_Vbus
    242
  - B_Sess
    242
- OTG and Host Mode Operation
  261
- Host Mode Operation Examples
  262
  - OTG Dual Role a Device Operation
    264
- On-The-Go Operation
  264
  - OTG Dual Role B Device Operation
    266
  - Power
    267
  - USB Suspend State
    268
  - Introduction
    269
- Chapter 16 Edge Port Module (EPORT)
  
  269
  - Interrupt/Gpio Pin Descriptions
    270
  - Low-Power Mode Operation
    270
    
    EPORT Pin Assignment Register (EPPAR)
    271
    
    Edge Port Interrupt Enable Register (EPIER)
    272
    
    EPORT Data Direction Register (EPDDR)
    272
    
    Edge Port Data Register (EPDR)
    273
    
    Edge Port Pin Data Register (EPPDR)
    273
    
    Edge Port Flag Register (EPFR)
    274
    
    Introduction
    275
    
    Overview
    275
- Chapter 17 DMA Controller Module
  
  275
  - Memory Map/Register Definition
    270
  - Features
    276
  - DMA Transfer Overview
    277
    
    DMA Request Control (DMAREQC)
    278
    
    Destination Address Registers (Darn)
    279
    
    Source Address Registers (Sarn)
    279
    
    Byte Count Registers (Bcrn) and DMA Status Registers (Dsrn)
    280
    
    DMA Control Registers (Dcrn)
    282
    
    Functional Description
    285
    
    Dual-Address Data Transfer Mode
    286
    
    Transfer Requests (Cycle-Steal and Continuous Modes)
    286
    
    Channel Initialization and Startup
    287
    
    Channel Prioritization
    287
    
    Auto-Alignment
    288
    
    Bandwidth Control
    288
    
    Data Transfer
    288
    
    Termination
    289
    
    Introduction
    291
    
    Overview
    291
  - Memory Map/Register Definition
    277
  - Features
    292
    
    External Signal Description
    293
    
    Memory Map and Register Definition
    293
    
    Flash Base Address Register (FLASHBAR)
    294
    
    Register Descriptions
    297
    
    Functional Description
    306
    
    General
    306
    
    Flash Normal Mode
    307
    
    Read Operation
    307
    
    Write Operation
    307
    
    Command Write Sequence
    308
    
    Page Erase
    314
    
    Flash Security Operation
    320
    
    Blank Check
    321
    
    Features
    323
    
    Modes of Operation
    323
    
    Overview
    324
- Chapter 19 Detailed Signal Descriptions
  
  324
  - External Signal Description
    324
  - Command Definition
    325
    
    Command Descriptions
    326
    
    Read Status Register
    326
    
    Functional Description
    329
    
    Reset Chip
    329
    
    Sector Erase
    329
  - Initialization/Application Information
    330
    
    Block Diagram
    331
    
    Introduction
    331
    
    Low-Power Mode Operation
    331
    
    Overview
    331
    
    Memory Map/Register Definition
    332
- Chapter 20
  
  333
  - PIT Control and Status Register (Pcsrn)
    333
  - PIT Modulus Register (Pmrn)
    334
  - Functional Description
    335
  - PIT Count Register (Pcntrn)
    335
  - Set-And-Forget Timer Operation
    335
  - Free-Running Timer Operation
    336
  - Interrupt Operation
    336
  - Timeout Specifications
    336
    
    Features
    339
    
    Introduction
    339
    
    Block Diagram
    340
    
    Low-Power Mode Operation
    341
  - Signal Description
    341
    
    Gpt3
    341
    
    Gpt[2:0]
    341
    
    Memory Map and Registers
    342
    
    Syncn
    342
    
    GPT Input Capture/Output Compare Select Register (GPTIOS)
    343
    
    GPT Compare Force Register (GPCFORC)
    344
    
    GPT Output Compare 3 Mask Register (GPTOC3M)
    344
    
    GPT Counter Register (GPTCNT)
    345
    
    GPT Output Compare 3 Data Register (GPTOC3D)
    345
    
    GPT System Control Register 1 (GPTSCR1)
    346
    
    GPT Control Register 1 (GPTCTL1)
    347
    
    GPT Toggle-On-Overflow Register (GPTTOV)
    347
    
    GPT Control Register 2 (GPTCTL2)
    348
    
    GPT Interrupt Enable Register (GPTIE)
    348
    
    GPT System Control Register 2 (GPTSCR2)
    349
    
    GPT Flag Register 1 (GPTFLG1)
    350
    
    GPT Flag Register 2 (GPTFLG2)
    350
    
    GPT Channel Registers (Gptcn)
    351
    
    Pulse Accumulator Control Register (GPTPACTL)
    351
    
    Pulse Accumulator Flag Register (GPTPAFLG)
    352
    
    Pulse Accumulator Counter Register (GPTPACNT)
    353
    
    Functional Description
    354
    
    GPT Port Data Direction Register (GPTDDR)
    354
    
    GPT Port Data Register (GPTPORT)
    354
    
    Input Capture
    355
    
    Output Compare
    355
    
    Prescaler
    355
    
    Event Counter Mode
    356
    
    Gated Time Accumulation Mode
    356
    
    Pulse Accumulator
    356
    
    General-Purpose I/O Ports
    357
    
    GPT Channel Interrupts (Cnf)
    359
    
    Pulse Accumulator Overflow (PAOVF)
    359
  - Interrupts
    359
  - Reset
    359
    
    Pulse Accumulator Input (PAIF)
    360
    
    Timer Overflow (TOF)
    360
  - Introduction
    361
    
    Overview
    361
- Chapter 22 DMA Timers (DTIM0-DTIM3)
  
  361
  - Features
    362
  - Memory Map/Register Definition
    362
    
    DMA Timer Mode Registers (Dtmrn)
    363
    
    DMA Timer Extended Mode Registers (Dtxmrn)
    364
    
    DMA Timer Event Registers (Dtern)
    365
    
    DMA Timer Reference Registers (Dtrrn)
    366
    
    DMA Timer Capture Registers (Dtcrn)
    367
    
    DMA Timer Counters (Dtcnn)
    367
    
    Capture Mode
    368
    
    Output Mode
    368
    
    Prescaler
    368
    
    Reference Compare
    368
  - Functional Description
    368
  - Initialization/Application Information
    369
    
    Code Example
    369
    
    Calculating Time-Out Values
    370
- Chapter 18
  
  371
  - Introduction
    371
    
    Block Diagram
    371
- Chapter 23 Queued Serial Peripheral Interface (QSPI)
  
  371
  - External Signal Description
    372
  - Features
    372
  - Modes of Operation
    372
  - Overview
    372
  - Memory Map/Register Definition
    373
  - QSPI Mode Register (QMR)
    373
  - QSPI Delay Register (QDLYR)
    375
  - QSPI Interrupt Register (QIR)
    376
  - QSPI Wrap Register (QWR)
    376
  - QSPI Address Register (QAR)
    377
  - Command RAM Registers (QCR0–QCR15)
    378
  - QSPI Data Register (QDR)
    378
  - Functional Description
    379
    
    Qspi Ram
    381
    
    Receive RAM
    381
    
    Baud Rate Selection
    382
    
    Command RAM
    382
    
    Transmit RAM
    382
    
    Transfer Delays
    383
    
    Data Transfer
    384
    
    Transfer Length
    384
    
    Initialization/Application Information
    385
    
    Introduction
    387
    
    Overview
    387
- Chapter 24 UART Modules
  
  387
  - Features
    388
  - External Signal Description
    389
    
    UART Mode Registers 1 (Umr1N)
    391
    
    UART Mode Register 2 (Umr2N)
    392
    
    UART Status Registers (Usrn)
    393
    
    UART Clock Select Registers (Ucsrn)
    395
    
    UART Command Registers (Ucrn)
    395
    
    UART Receive Buffers (Urbn)
    397
    
    UART Input Port Change Registers (Uipcrn)
    398
    
    UART Transmit Buffers (Utbn)
    398
    
    UART Auxiliary Control Register (Uacrn)
    399
    
    UART Interrupt Status/Mask Registers (Uisrn/Uimrn)
    399
    
    UART Baud Rate Generator Registers (Ubg1N/Ubg2N)
    401
    
    UART Input Port Register (Uipn)
    401
    
    Functional Description
    402
    
    Transmitter/Receiver Clock Source
    402
    
    UART Output Port Command Registers (Uop1N/Uop0N)
    402
    
    Calculating Baud Rates
    403
    
    Programmable Divider
    403
    
    External Clock
    404
    
    Transmitter and Receiver Operating Modes
    404
    
    Looping Modes
    408
    
    Automatic Echo Mode
    409
    
    Local Loopback Mode
    409
    
    Remote Loopback Mode
    409
    
    Multidrop Mode
    410
    
    Bus Operation
    412
    
    Initialization/Application Information
    412
    
    Interrupt and DMA Request Initialization
    412
    
    UART Module Initialization Sequence
    414
    
    Introduction
    421
- Chapter 25 I 2 C Interface
  
  421
  - Memory Map/Register Definition
    389
  - Block Diagram
    422
    
    Features
    423
  - Overview
    422
  - Memory Map/Register Definition
    423
    
    Functional Description
    428
    
    START Signal
    428
    
    Data Transfer
    429
    
    Slave Address Transmission
    429
    
    Acknowledge
    430
    
    Repeated START
    430
    
    STOP Signal
    430
    
    Clock Synchronization and Arbitration
    432
    
    Generation of START
    433
    
    Handshaking and Clock Stretching
    433
    
    Initialization Sequence
    433
    
    Initialization/Application Information
    433
    
    Generation of STOP
    434
    
    Post-Transfer Software Response
    434
    
    Arbitration Lost
    435
    
    Generation of Repeated START
    435
    
    Slave Mode
    435
- Chapter 26 Analog-To-Digital Converter (ADC)
  
  437
  - Block Diagram
    438
  - Control 1 Register (CTRL1)
    439
  - Control 2 Register (CTRL2)
    441
  - Channel List 1 and 2 Registers (ADLST1 and ADLST2)
    444
  - Zero Crossing Control Register (ADZCC)
    444
  - Sample Disable Register (ADSDIS)
    446
  - Status Register (ADSTAT)
    447
  - Limit Status Register (ADLSTAT)
    449
  - Result Registers (Adrsltn)
    450
  - Zero Crossing Status Register (ADZCSTAT)
    450
  - Low and High Limit Registers (Adllmtn and Adhlmtn)
    451
  - Offset Registers (Adofsn)
    453
  - Power Control Register (POWER)
    453
  - Voltage Reference Register (CAL)
    456
  - Functional Description
    457
  - Input MUX Function
    459
  - ADC Sample Conversion
    461
  - ADC Data Processing
    463
  - Sequential Vs. Parallel Sampling
    464
  - Scan Sequencing
    465
  - Scan Configuration and Control
    466
  - Interrupt Sources
    468
  - Power Management Modes
    468
  - ADC Clock
    470
  - Supply Pins
    474
- Chapter 27 Pulse-Width Modulation (PWM) Module
  
  475
  - Introduction
    475
  - Overview
    475
  - Memory Map/Register Definition
    476
  - PWM Enable Register (PWME)
    477
  - PWM Clock Select Register (PWMCLK)
    478
  - PWM Polarity Register (PWMPOL)
    478
  - PWM Prescale Clock Select Register (PWMPRCLK)
    479
  - PWM Center Align Enable Register (PWMCAE)
    480
  - PWM Control Register (PWMCTL)
    481
  - PWM Scale a Register (PWMSCLA)
    482
  - PWM Channel Counter Registers (Pwmcntn)
    483
  - PWM Scale B Register (PWMSCLB)
    483
  - PWM Channel Period Registers (Pwmpern)
    484
  - PWM Channel Duty Registers (Pwmdtyn)
    485
  - PWM Shutdown Register (PWMSDN)
    486
  - Functional Description
    487
  - PWM Clock Select
    487
  - Clock Select
    489
  - PWM Channel Timers
    489
  - Block Diagram
    497
- Chapter 28 Debug Module
  
  497
  - Introduction
    497
  - Overview
    497
  - Signal Descriptions
    498
  - Real-Time Trace Support
    499
    
    Begin Execution of Taken Branch (PST = 0X5)
    501
    
    Memory Map/Register Definition
    502
    
    Configuration/Status Register (CSR)
    503
    
    Shared Debug Resources
    503
    
    Address Attribute Trigger Register (AATR)
    506
    
    BDM Address Attribute Register (BAAR)
    506
    
    Trigger Definition Register (TDR)
    508
    
    Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR)
    511
    
    Address Breakpoint Registers (ABLR, ABHR)
    513
    
    Data Breakpoint and Mask Registers (DBR, DBMR)
    514
  - Background Debug Mode (BDM)
    515
    
    CPU Halt
    515
    
    BDM Serial Interface
    516
    
    Receive Packet Format
    517
    
    BDM Command Set
    518
    
    Transmit Packet Format
    518
    
    Coldfire BDM Command Format
    520
    
    Extension Words as Required
    520
    
    Command Sequence Diagrams
    521
    
    Command Set Descriptions
    522
    
    Resume Execution
    529
  - Real-Time Debug Support
    535
    
    Theory of Operation
    535
    
    Concurrent BDM and Processor Operation
    537
    
    Emulator Mode
    537
  - Processor Status, Debug Data Definition
    538
    
    User Instruction Set
    538
  - Freescale-Recommended BDM Pinout
    543
    
    Supervisor Instruction Set
    543
    
    Block Diagram
    545
    
    Introduction
    545
- Chapter 29 IEEE 1149.1 Test Access Port (JTAG)
  
  545
  - External Signal Description
    546
  - Features
    546
  - JTAG Enable (JTAG_EN)
    546
  - Modes of Operation
    546
  - Test Clock Input (TCLK)
    547
  - Test Data Input/Development Serial Input (TDI/DSI)
    547
  - Test Mode Select/Breakpoint (TMS/BKPT)
    547
  - IDCODE Register
    548
  - Instruction Shift Register (IR)
    548
  - Memory Map/Register Definition
    548
  - Test Data Output/Development Serial Output (TDO/DSO)
    548
  - Test Reset/Development Serial Clock (TRST/DSCLK)
    548
  - Boundary Scan Register
    549
  - Bypass Register
    549
  - JTAG_CFM_CLKDIV Register
    549
  - TEST_CTRL Register
    549
  - Functional Description
    550
    
    JTAG Module
    550
    
    TAP Controller
    550
    
    JTAG Instructions
    551
    
    IDCODE Instruction
    552
    
    SAMPLE/PRELOAD Instruction
    552
    
    BYPASS Instruction
    554
    
    Initialization/Application Information
    554
    
    Nonscan Chain Operation
    554
    
    Restrictions
    554
- Appendix A Register Memory Map Quick Reference
  
  555
  - B.1 Changes between Rev. 1 and Rev. 2
    575
  - B.2 Changes between Rev. 0 and Rev. 1
    576

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Motherboard Computer Hardware Microcontrollers Control Unit Controller

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Table of Contents

Signal Descriptions

Chapter 1 Overview

Chapter 7 Backup Watchdog Timer

Chapter 2 Signal Descriptions

Chapter 3 Coldfire Core

Chapter 4

Chapter 5 Static RAM (SRAM)

Chapter 21

Chapter 6 Clock Module

Chapter 8 Power Management

Chapter 9 Chip Configuration Module (CCM)

Chapter 10 Reset Controller Module

Chapter 11 Real-Time Clock

Chapter 12 System Control Module (SCM)

Chapter 13 General Purpose I/O Module

Chapter 14 Interrupt Controller Theory of Operation

Chapter 15

15.4.1.5 Otg Interrupt Status Register (Otg_Int_Stat)

Chapter 16 Edge Port Module (EPORT)

Chapter 17 DMA Controller Module

Chapter 19 Detailed Signal Descriptions

Chapter 20

Chapter 22 DMA Timers (DTIM0-DTIM3)

Chapter 18

Chapter 23 Queued Serial Peripheral Interface (QSPI)

Chapter 24 UART Modules

Chapter 25 I 2 C Interface

Chapter 26 Analog-To-Digital Converter (ADC)

Chapter 27 Pulse-Width Modulation (PWM) Module

Chapter 28 Debug Module

Chapter 29 IEEE 1149.1 Test Access Port (JTAG)

Appendix A Register Memory Map Quick Reference

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