Extended Trigger Definition Register (Xtdr) - Freescale Semiconductor MCF54455 Reference Manual

DRc[4:0]: 0x14 (PBASID)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
PBA3SID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–24 Corresponds to the ASID associated with PBR3.
PBR3ASID
23–16 Corresponds to the ASID associated with PBR2.
PBR2ASID
15–8 Corresponds to the ASID associated with PBR1.
PBR1ASID
7–0 Corresponds to the ASID associated with PBR0.
PBR0ASID

34.3.11 Extended Trigger Definition Register (XTDR)

The XTDR configures the operation of the hardware breakpoint logic that corresponds with the
ABHR1/ABLR1/AATR1, DBR1/DBMR1 registers within the debug module. In conjunction with the
TDR and its associated debug registers, XTDR controls the actions taken under the defined conditions.
Breakpoint logic may be configured as a one- or two-level triggers. TDR[31–16] or XTDR[31–16] bits
define second-level triggers, and bits 15–0 define first-level triggers.
The debug module has no hardware interlocks; so to prevent spurious
breakpoint triggers while the breakpoint registers are being loaded, disable
TDR and XTDR (by clearing TDR[29,13] and XTDR[29,13]) before
defining triggers.
A write to XTDR clears the CSR trigger status bits, CSR[BSTAT]. XTDR is accessible in supervisor mode
using the WDEBUG instruction and through the BDM port using the
Section 34.3.11.1, "Resulting Set of Possible Trigger
breakpoint conditions.
Freescale Semiconductor
PBA2SID
Figure 34-14. PC Breakpoint ASID Register (PBASID)
Table 34-20. PBASID Field Descriptions
NOTE
Access: Supervisor read/write
8
PBA1SID
Description
WDMREG
Combinations," describes how to handle multiple
Debug Module
BDM read/write
7 6 5 4 3 2 1 0
PBA0SID
command.
34-22