Table of Contents
Advertisement
FlexBus
•
Byte-, word-, longword-, and 16-byte line-sized transfers
•
Programmable burst- and burst-inhibited transfers selectable for each chip select and transfer
direction
•
Programmable address-setup time with respect to the assertion of chip select
•
Programmable address-hold time with respect to the negation of chip select and transfer direction
20.1.3
Modes of Operation
The external interface is a configurable multiplexed bus set to one of the following modes:
•
Multiplexed 32-bit address and 32-bit data
•
Multiplexed 32-bit address and 16-bit data (non-multiplexed 16-bit address and 16-bit data)
•
Multiplexed 32-bit address and 8-bit data (non-multiplexed 24-bit address and 8-bit data)
•
Non-multiplexed 32-bit address with 32-bit data
While using non-multiplexed 32-bit mode, the PCI address/data bus is used
as the FlexBus address bus. See
(CCM),"
20.2
External Signals
This section describes the external signals involved in data-transfer operations.
Signal Name
FB_A[31:0]
FB_D[31:0]
FB_CS[5:0]
FB_BE/BWE[3:0]
FB_OE
FB_R/W
FB_ALE
FB_TSIZ[1:0]
FB_TBST
FB_TA
20-2
Chapter 11, "Chip Configuration Module
for more information.
Table 20-1. FlexBus Signal Summary
1
I/O
O
In a non-multiplexed configuration: Address bus.
In a multiplexed configuration: Not used.
I/O
In a non-multiplexed configuration: Data bus.
In a multiplexed configuration: Address/data bus, FB_AD[31:0].
O
General purpose chip-selects. The actual number of chip selects available
depends upon the device and its pin configuration. See
for more details.
O
Byte enable/byte write enable
O
Output enable
O
Read/write. 1 = Read, 0 = Write
O
Address latch enable
O
Transfer size
O
Burst transfer indicator
I
Transfer acknowledge
NOTE
Description
Table 1-1Table 2-2
Freescale Semiconductor
Advertisement
Table of Contents
