Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual

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MPC8260 PowerQUICC™ II

Family Reference Manual

Supports

MPC8250

MPC8255

MPC8260

MPC8264

MPC8265

MPC8266

MPC8260RM

Rev. 2, 12/2005

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Page 1 MPC8260 PowerQUICC™ II Family Reference Manual Supports MPC8250 MPC8255 MPC8260 MPC8264 MPC8265 MPC8266 MPC8260RM Rev. 2, 12/2005...
Page 2 Freescale Semiconductor product For Literature Requests Only: could create a situation where personal injury or death may occur. Should Buyer...
Page 3 Part I—Overview Overview G2 Core Memory Map Part II—Configuration and Reset System Interface Unit (SIU) Reset Part III—The Hardware Interface External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.1 Test Access Port Part IV—Communications Processor Module Communications Processor Module Overview Serial Interface with Time-Slot Assigner...
Page 4 Part I—Overview Overview G2 Core Memory Map Part II—Configuration and Reset System Interface Unit (SIU) Reset Part III—The Hardware Interface External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.1 Test Access Port Part IV—Communications Processor Module Communications Processor Module Overview Serial Interface with Time-Slot Assigner...
Page 5 Fast Ethernet Controller FCC HDLC Controller FCC Transparent Controller Serial Peripheral Interface (SPI) C Controller Parallel I/O Ports Register Quick Reference Guide Reference Manual (Rev 1) Errata Glossary of Terms and Abbreviations Index...
Page 6 Fast Ethernet Controller FCC HDLC Controller FCC Transparent Controller Serial Peripheral Interface (SPI) C Controller Parallel I/O Ports Register Quick Reference Guide Reference Manual (Rev 1) Errata Glossary of Terms and Abbreviations Index...
Page 7: Table Of Contents
Telecommunications Switch Controller ..............1-18 1.7.1.6 SONET Transmission Controller................1-18 1.7.2 Bus Configurations ....................1-19 1.7.2.1 Basic System......................1-19 1.7.2.2 High-Performance Communication............... 1-20 1.7.2.3 High-Performance System Microprocessor............1-21 1.7.2.4 PCI ......................... 1-21 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 8 PowerQUICC II Implementation-Specific Cache Implementation ......2-18 2.4.2.1 Data Cache......................2-18 2.4.2.2 Instruction Cache ....................2-20 2.4.2.3 Cache Locking ....................... 2-20 2.4.2.3.1 Entire Cache Locking ..................2-20 2.4.2.3.2 Way Locking...................... 2-20 Exception Model......................2-21 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 9 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L) ......4-19 4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L) ........ 4-21 4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)........4-22 4.3.1.6 SIU Interrupt Vector Register (SIVEC) ..............4-24 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 10 Reset Mode Register (RMR) ................... 5-5 Reset Configuration ......................5-6 5.4.1 Hard Reset Configuration Word .................. 5-8 5.4.2 Hard Reset Configuration Examples ................. 5-10 5.4.2.1 Single PowerQUICC II with Default Configuration ..........5-10 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 viii Freescale Semiconductor...
Page 11 7.2.4.1.1 Transfer Type (TT[0–4])—Output............... 7-7 7.2.4.1.2 Transfer Type (TT[0–4])—Input ................. 7-7 7.2.4.2 Transfer Size (TSIZ[0–3]) ..................7-7 7.2.4.3 Transfer Burst (TBST)..................... 7-8 7.2.4.4 Global (GBL)......................7-8 7.2.4.4.1 Global (GBL)—Output..................7-8 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 12 7.2.8.3.1 Partial Data Valid (PSDVAL)—Input..............7-16 7.2.8.3.2 Partial Data Valid (PSDVAL)—Output ............. 7-17 Chapter 8 The 60x Bus Terminology........................8-1 Bus Configuration......................8-2 8.2.1 Single-PowerQUICC II Bus Mode ................8-2 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 13 8.7.2 TLBISYNC Input ...................... 8-32 Little-Endian Mode......................8-32 Chapter 9 PCI Bridge Signals..........................9-3 Clocking........................... 9-3 PCI Bridge Initialization ....................9-3 SDMA Interface....................... 9-3 Interrupts from PCI Bridge ....................9-4 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 14 9.11.1.1 Message Unit (I2O) Registers ................9-30 9.11.1.2 DMA Controller Registers..................9-30 9.11.1.3 PCI Outbound Translation Address Registers (POTARx) ........9-30 9.11.1.4 PCI Outbound Base Address Registers (POBARx) ..........9-31 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 15 PCI Bus Arbiter Configuration Register ............... 9-59 9.11.2.24 PCI Hot Swap Register Block ................9-60 9.11.2.25 PCI Hot Swap Control Status Register ..............9-61 9.11.2.26 PCI Configuration Register Access from the Core ..........9-62 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor xiii...
Page 16 DMA Chaining Mode .................... 9-86 9.13.1.3 DMA Coherency....................9-87 9.13.1.4 Halt and Error Conditions..................9-87 9.13.1.5 DMA Transfer Types ..................... 9-87 9.13.1.6 DMA Registers ...................... 9-88 9.13.1.6.1 DMA Mode Register [0–3] (DMAMRx) ............9-88 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 17 PCI Bridge as an Agent Operating from the PCI System Clock ......10-3 10.4.3.2 PCI Bridge as a Host and Generating the PCI System Clock........ 10-4 10.4.3.2.1 CPM CLOCK and PCI Frequency Equations ........... 10-5 10.5 Clock Dividers ....................... 10-5 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 18 Memory Refresh Timer Prescaler Register (MPTPR) ..........11-32 11.3.13 60x Bus Error Status and Control Registers (TESCRx) .......... 11-33 11.3.14 Local Bus Error Status and Control Registers (L_TESCRx) ........11-33 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 19 Differences between MPC8xx’s GPCM and MPC82xx’s GPCM......11-63 11.6 User-Programmable Machines (UPMs)............... 11-63 11.6.1 Requests ........................11-64 11.6.1.1 Memory Access Requests..................11-66 11.6.1.2 UPM Refresh Timer Requests ................11-66 11.6.1.3 Software Requests—run Command ..............11-67 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor xvii...
Page 20 ECC/Parity Mode....................... 12-4 12.2 L2 Cache Interface Parameters ..................12-6 12.3 System Requirements When Using the L2 Cache Interface.......... 12-7 12.4 L2 Cache Operation ....................... 12-7 12.5 Timing Example......................12-7 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 xviii Freescale Semiconductor...
Page 21 RISC Timer Command Register (TM_CMD) ............14-24 14.6.3 RISC Timer Table Entries..................14-24 14.6.4 RISC Timer Event Register (RTER)/Mask Register (RTMR) ........ 14-24 14.6.5 set timer Command....................14-25 14.6.6 RISC Timer Initialization Sequence ................ 14-25 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 22 Enabling Connections to TSA or NMSI ................ 16-3 16.3 NMSI Configuration ...................... 16-4 16.4 CMX Registers ......................16-7 16.4.1 CMX UTOPIA Address Register (CMXUAR) ............16-7 16.4.2 CMX SI1 Clock Route Register (CMXSI1CR)............16-12 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 23 IDMA Features ......................19-5 19.5 IDMA Transfers......................19-6 19.5.1 Memory-to-Memory Transfers .................. 19-6 19.5.1.1 External Request Mode..................19-8 19.5.1.2 Normal Mode......................19-9 19.5.1.3 Working with a PCI Bus ..................19-9 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 24 Memory-to-Memory (PCI Bus to 60x Bus)—IDMA1 ..........19-33 Chapter 20 Serial Communications Controllers (SCCs) 20.1 Features .......................... 20-2 20.1.1 The General SCC Mode Registers (GSMR1–GSMR4) ..........20-3 20.1.2 Protocol-Specific Mode Register (PSMR) ..............20-9 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 xxii Freescale Semiconductor...
Page 25 Fractional Stop Bits (Transmitter) ................21-10 21.15 Handling Errors in the SCC UART Controller ............21-11 21.16 UART Mode Register (PSMR)..................21-12 21.17 SCC UART Receive Buffer Descriptor (RxBD) ............21-14 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor xxiii...
Page 26 SCC BISYNC Mode 23.1 Features .......................... 23-2 23.2 SCC BISYNC Channel Frame Transmission ..............23-2 23.3 SCC BISYNC Channel Frame Reception ..............23-3 23.4 SCC BISYNC Parameter RAM ..................23-3 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 xxiv Freescale Semiconductor...
Page 27 SCC Transparent Transmit Buffer Descriptor (TxBD)..........24-10 24.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)......24-11 24.13 SCC Status Register in Transparent Mode (SCCS) ............. 24-12 24.14 SCC2 Transparent Programming Example..............24-12 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 28 Programming the SCC in AppleTalk Mode..............26-3 26.4.1 Programming the GSMR ................... 26-3 26.4.2 Programming the PSMR.................... 26-4 26.4.3 Programming the TODR.................... 26-4 26.4.4 SCC AppleTalk Programming Example..............26-4 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 xxvi Freescale Semiconductor...
Page 29 27.4.7 Handling Errors in the SMC Transparent Controller..........27-25 27.4.8 SMC Transparent RxBD..................27-26 27.4.9 SMC Transparent TxBD ..................27-27 27.4.10 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)...... 27-28 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor xxvii...
Page 30 28.3.4 Channel-Specific SS7 Parameters ................28-17 28.3.4.1 Extended Channel Mode Register (ECHAMR)—SS7 Mode......28-21 28.3.4.2 Signal Unit Error Monitor (SUERM)—SS7 Mode ..........28-23 28.3.4.2.1 SUERM in Japanese SS7................. 28-23 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 xxviii Freescale Semiconductor...
Page 31 MCC Initialization and Start/Stop Sequence ............... 28-47 28.10.1 Stopping and Restarting a Single-Channel .............. 28-48 28.10.2 Stopping and Restarting a Superchannel ..............28-49 28.11 MCC Latency and Performance .................. 28-49 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor xxix...
Page 32 ATM Controller Overview..................... 30-4 30.2.1 Transmitter Overview ....................30-5 30.2.1.1 AAL5 Transmitter Overview................. 30-5 30.2.1.2 AAL1 Transmitter Overview................. 30-5 30.2.1.2.1 AAL1 CES Transmitter Overview ..............30-6 30.2.1.3 AAL0 Transmitter Overview................. 30-6 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 33 ABR Flow Control Destination End-System Behavior ........30-21 30.5.1.3 ABR Flowcharts ....................30-21 30.5.2 RM Cell Structure....................30-25 30.5.2.1 RM Cell Rate Representation ................30-26 30.5.3 ABR Flow Control Setup..................30-27 30.6 OAM Support ......................30-27 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor xxxi...
Page 34 Transmit Connection Table (TCT)............... 30-50 30.10.2.3.1 AAL5 Protocol-Specific TCT ................. 30-55 30.10.2.3.2 AAL1 Protocol-Specific TCT ................. 30-55 30.10.2.3.3 AAL0 Protocol-Specific TCT ................. 30-57 30.10.2.3.4 AAL1 CES Protocol-Specific TCT ..............30-57 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 xxxii Freescale Semiconductor...
Page 35 UTOPIA Interface Master Mode ................30-84 30.12.1.1 UTOPIA Master Multiple PHY Operation............30-85 30.12.2 UTOPIA Interface Slave Mode ................30-86 30.12.2.1 UTOPIA Slave Multiple PHY Operation ............30-87 30.12.2.2 UTOPIA Clocking Modes ................... 30-87 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor xxxiii...
Page 36 ATM-to-TDM Adaptive Slip Control ................31-15 31.5.1 CES Adaptive Threshold Tables................31-16 31.6 3-Step-SN Algorithm ....................31-20 31.6.1 The Three States of the Algorithm ................31-20 31.7 Pointer Verification Mechanism .................. 31-21 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 xxxiv Freescale Semiconductor...
Page 37 CPS Tx Queue Descriptor ................... 32-13 32.3.5.3 CPS Buffer Structure ................... 32-15 32.3.5.4 SSSAR Tx Queue Descriptor ................32-17 32.3.5.5 SSSAR Transmit Buffer Descriptor..............32-19 32.4 AAL2 Receiver ......................32-20 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor xxxv...
Page 38 Plane Management Functions Performed by Microcode........33-11 33.3.2 Transmit Architecture ....................33-11 33.3.2.1 TRL Operation..................... 33-12 33.3.2.1.1 TRL Service Latency..................33-13 33.3.2.2 Non-TRL Operation..................... 33-13 33.3.2.3 Transmit Queue Operation Examples (ITC mode)..........33-14 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 xxxvi Freescale Semiconductor...
Page 39 IMA Link Receive Control (ILRCNTL) ............33-46 33.4.5.2.2 IMA Link Receive State (ILRSTATE) ............33-47 33.4.5.3 IMA Link Receive Statistics Table..............33-48 33.4.6 Structures in External Memory................33-48 33.4.6.1 Transmit Queues ....................33-48 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor xxxvii...
Page 40 33.5.4 IMA Software Procedures ..................33-62 33.5.4.1 Transmit ICP Cell Signalling................33-62 33.5.4.2 Receive Link Start-up Procedure................. 33-62 33.5.4.3 Group Start-up Procedure ................... 33-63 33.5.4.3.1 As Initiator (TX)....................33-64 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 xxxviii Freescale Semiconductor...
Page 41 Cell Delineation State Machine Register [1–8] (CDSMRx)........34-9 34.4.1.3 TC Layer Event Register [1–8] (TCERx)............34-10 34.4.1.4 TC Layer Mask Register (TCMRx)..............34-11 34.4.2 TC Layer General Registers ..................34-11 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor xxxix...
Page 42 Programming Model ....................35-11 35.10 Ethernet Command Set ....................35-11 35.11 RMON Support......................35-13 35.12 Ethernet Address Recognition ..................35-14 35.13 Hash Table Algorithm....................35-16 35.14 Interpacket Gap Time....................35-17 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 43 37.3.3 Transparent Synchronization Example ..............37-3 Chapter 38 Serial Peripheral Interface (SPI) 38.1 Features .......................... 38-1 38.2 SPI Clocking and Signal Functions ................38-2 38.3 Configuring the SPI Controller..................38-3 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 44 C Buffer Descriptor (BD) Table ................ 39-11 39.7.1 C Buffer Descriptors (BDs) .................. 39-12 39.7.1.1 C Receive Buffer Descriptor (RxBD)............... 39-12 39.7.1.2 C Transmit Buffer Descriptor (TxBD) ............. 39-13 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 xlii Freescale Semiconductor...
Page 45 PowerPC Registers—User Registers ................A-1 PowerPC Registers—Supervisor Registers ..............A-1 MPC8260-Specific SPRs ....................A-3 Appendix B Reference Manual (Rev 1) Errata Document Errata ......................B-1 Glossary of Terms and Abbreviations MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor xliii...
Page 46 Contents Paragraph Page Number Title Number MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 xliv Freescale Semiconductor...
Page 47 CPM Low Interrupt Priority Register (SCPRR_L)............... 4-20 4-14 SIPNR_H ..........................4-21 4-15 SIPNR_L ..........................4-22 4-16 SIMR_H ..........................4-23 4-17 SIMR_L ..........................4-23 4-18 SIU Interrupt Vector Register (SIVEC) ................4-24 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 48 Address Bus Arbitration with External Bus Master..............8-8 Address Pipelining ........................8-9 Interface to Different Port Size Devices ................8-17 Retry Cycle ........................... 8-23 Single-Beat and Burst Data Transfers................... 8-27 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 xlvi Freescale Semiconductor...
Page 49 PCI Inbound Comparison Mask Registers (PICMRx)............9-44 9-32 PCI Bridge PCI Configuration Registers ................9-46 9-33 Vendor ID Register........................ 9-47 9-34 Device ID Register........................ 9-47 9-35 PCI Bus Command Register ....................9-47 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor xlvii...
Page 50 Inbound FIFO Queue Port Register (IFQPR) ............... 9-77 9-74 Outbound FIFO Queue Port Register (OFQPR) ..............9-78 9-75 Outbound Message Interrupt Status Register (OMISR) ............9-79 9-76 Outbound Message Interrupt Mask Register (OMIMR)............9-80 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 xlviii Freescale Semiconductor...
Page 51 Memory Refresh Timer Prescaler Register (MPTPR) ............11-32 11-19 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown) ......11-34 11-20 PRETOACT = 2 (2 Clock Cycles)..................11-39 11-21 ACTTORW = 2 (2 Clock Cycles)..................11-40 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor xlix...
Page 52 Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1) Clock Ratios..11-68 11-60 UPM Signals Timing Example ................... 11-69 11-61 RAM Array and Signal Generation ..................11-70 11-62 The RAM Word........................11-70 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 53 RISC Controller Configuration Register (RCCR..............14-9 14-4 RISC Time-Stamp Control Register (RTSCR) ..............14-11 14-5 RISC Time-Stamp Register (RTSR) ................... 14-12 14-6 CP Command Register (CPCR)..................14-13 14-7 Dual-Port RAM Block Diagram ..................14-18 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 54 CMX FCC Clock Route Register (CMXFCR) ..............16-14 16-11 CMX SCC Clock Route Register (CMXSCR) ..............16-16 16-12 CMX SMC Clock Route Register (CMXSMR) ..............16-19 17-1 Baud-Rate Generator (BRG) Block Diagram ............... 17-1 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 55 DPLL Encoding Examples....................20-23 21-1 UART Character Format ....................... 21-1 21-2 Two UART Multidrop Configurations.................. 21-7 21-3 Control Character Table ......................21-8 21-4 Transmit Out-of-Sequence Register (TOSEQ) ..............21-9 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor liii...
Page 56 24-5 SCC Status Register in Transparent Mode (SCCS) ............24-12 25-1 Ethernet Frame Structure ...................... 25-1 25-2 Ethernet Block Diagram......................25-2 25-3 Connecting the PowerQUICC II to Ethernet ................ 25-4 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 57 Extended Channel Mode Register (ECHAMR)..............28-22 28-10 SS7 Configuration Register (SS7_OPT) ................28-24 28-11 Mask1 Format ........................28-26 28-12 Mask2 Format ........................28-26 28-13 Super Channel Table Entry ....................28-29 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 58 Performance Monitoring Cell Structure (FMCs and BRCs)..........30-29 30-18 FMC, BRC Insertion ......................30-31 30-19 Format of User-Defined Cells..................... 30-32 30-20 External CAM Address in UDC Extended Address Mode..........30-33 30-21 ATM-to-TDM Interworking....................30-34 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 59 FCC ATM Mode Register (FPSMR) .................. 30-88 30-60 ATM Event Register (FCCE)/FCC Mask Register (FCCM) ..........30-91 30-61 FCC Transmit Internal Rate Registers (FTIRRx) ............... 30-92 30-62 FCC Transmit Internal Rate Clocking ................30-92 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor lvii...
Page 60 AAL2 Sublayer Structure...................... 32-2 32-3 AAL2 Switching Example ....................32-3 32-4 Round Robin Priority ......................32-6 32-5 Fixed Priority Mode ......................32-7 32-6 AAL2 Protocol-Specific Transmit Connection Table (TCT)..........32-9 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lviii Freescale Semiconductor...
Page 61 IMA Receive Group Frame Size (IGRSTATE) ..............33-40 33-20 Receive Group Order Table Entry..................33-40 33-21 IMA Link Transmit Control (ILTCNTL)................33-42 33-22 IMA Link Transmit State (ILTSTATE) ................33-43 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 62 FCC HDLC Receive Buffer Descriptor (RxBD) ..............36-11 36-6 FCC HDLC Transmit Buffer Descriptor (TxBD) ............... 36-12 36-7 HDLC Event Register (FCCE)/Mask Register (FCCM) ............ 36-14 36-8 HDLC Interrupt Event Example ..................36-16 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 63 Port Data Direction Register (PDIR) ..................40-3 40-4 Port Pin Assignment Register (PPARA–PPARD)..............40-4 40-5 Special Options Registers (PSORA–POSRD) ..............40-5 40-6 Port Functional Operation ..................... 40-6 40-7 Primary and Secondary Option Programming ..............40-8 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 64: Mpc8260 Powerquicc Ii Family Reference Manual, Rev
Figures Figure Page Number Title Number MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lxii Freescale Semiconductor...
Page 65 4-18 L_TESCR2 Field Descriptions ..................... 4-43 4-19 TMCNTSC Field Descriptions ..................... 4-44 4-20 TMCNTAL Field Descriptions ..................... 4-45 4-21 PISCR Field Descriptions ..................... 4-46 4-22 PITC Field Descriptions......................4-47 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor lxiii...
Page 66 ESR Field Descriptions ......................9-36 9-11 EMR Field Descriptions......................9-37 9-12 ECR Field Descriptions ......................9-39 9-13 PCI_EACR Field Descriptions ..................... 9-40 9-14 PCI_EDCR Field Description ....................9-40 9-15 PCI_ECCR Field Descriptions....................9-41 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lxiv Freescale Semiconductor...
Page 67 IFTPR Field Descriptions ..................... 9-72 9-52 IPHPR Field Descriptions ..................... 9-73 9-53 IPTPR Field Descriptions...................... 9-74 9-54 OFHPR Field Descriptions ....................9-75 9-55 OFTPR Field Descriptions....................9-75 9-56 OPHPR Field Descriptions ....................9-76 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 68 LSRT Field Descriptions..................... 11-32 11-17 MPTPR Field Descriptions ....................11-32 11-18 SDRAM Interface Signals ....................11-33 11-19 SDRAM Interface Commands .................... 11-36 11-20 SDRAM Address Multiplexing (A0–A15) ................. 11-38 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lxvi Freescale Semiconductor...
Page 69 TM_CMD Field Descriptions ..................... 14-24 15-1 SIx RAM Entry (MCC = 0) ....................15-11 15-2 SIx RAM Entry (MCC = 1) ....................15-13 15-3 SIx RAM Entry Descriptions....................15-14 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor lxvii...
Page 70 Parallel I/O Register Programming—Port D ..............19-30 19-15 Example: Peripheral-to-Memory Mode—IDMA2 ............. 19-30 19-16 Example: Memory-to-Peripheral Fly-By Mode (on 60x)–IDMA3 ........19-32 19-17 Programming Example: Memory-to-Memory (PCI-to-60x)—IDMA1......19-33 20-1 GSMR_H Field Descriptions ....................20-3 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lxviii Freescale Semiconductor...
Page 71 23-5 BSYNC Field Descriptions ....................23-8 23-6 BDLE Field Descriptions...................... 23-9 23-7 Receiver SYNC Pattern Lengths of the DSR................ 23-9 23-8 Transmit Errors ........................23-10 23-9 Receive Errors........................23-10 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor lxix...
Page 72 SMC Transparent Error Conditions ..................27-26 27-13 SMC Transparent RxBD Field Descriptions............... 27-26 27-14 SMC Transparent TxBD ..................... 27-27 27-15 SMC Transparent TxBD Field Descriptions............... 27-27 27-16 SMCE/SMCM Field Descriptions ..................27-29 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 73 Field Descriptions for Address Compression ..............30-16 30-4 VCOFFSET Calculation Examples for Contiguous VCLTs ..........30-16 30-5 VP-Level Table Entry Address Calculation Example............30-17 30-6 VC-Level Table Entry Address Calculation Example ............30-18 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor lxxi...
Page 74 30-44 UTOPIA Master Mode Signal Descriptions ............... 30-84 30-45 UTOPIA Slave Mode Signals ..................... 30-86 30-46 UTOPIA Loop-Back Modes ....................30-87 30-47 FCC ATM Mode Register (FPSMR) .................. 30-88 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lxxii Freescale Semiconductor...
Page 75 33-5 IMA Group Transmit Table Entry ..................33-30 33-6 IGTCNTL Field Descriptions ..................... 33-31 33-7 IGTSTATE Field Descriptions .................... 33-32 33-8 Transmit Group Order Table Entry Field Descriptions............33-33 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor lxxiii...
Page 76: Features
Transmit Commands ......................35-12 35-4 Receive Commands......................35-12 35-5 RMON Statistics and Counters ................... 35-13 35-6 Transmission Errors ......................35-18 35-7 Reception Errors ......................... 35-18 35-8 FPSMR Ethernet Field Descriptions................... 35-19 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lxxiv Freescale Semiconductor...
Page 77 Port B Dedicated Pin Assignment (PPARB = 1) ............... 40-12 40-7 Port C Dedicated Pin Assignment (PPARC = 1) ............... 40-14 40-8 Port D Dedicated Pin Assignment (PPARD = 1) .............. 40-17 User-Level PowerPC Registers (non-SPRs) ................A-1 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor lxxv...
Page 78 Tables Table Page Number Title Number User-Level PowerPC SPRs ....................A-1 Supervisor-Level PowerPC Registers ..................A-2 Supervisor-Level PowerPC SPRs ..................A-2 MPC8260-Specific Supervisor-Level SPRs ................A-3 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lxxvi Freescale Semiconductor...
Page 79: About This Book
Substantive differences between this revision and revision 1 of this manual are summarized in Table Users who are familiar with revision 1 should verify if a given portion has changed by referring to the corresponding portion in this current manual. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor lxxvii...
Page 80 “Multi-Channel Controllers specific devices. (MCCs)” Note: This notation format is also used within chapters to stress information that is common to all devices. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lxxviii Freescale Semiconductor...
Page 81 60x bus configuration. — Chapter 5, “Reset,” describes the behavior of the PowerQUICC II at reset and start-up. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor lxxix...
Page 82 WANs, LANs, and proprietary networks. — Chapter 21, “SCC UART Mode,” describes the PowerQUICC II implementation of universal asynchronous receiver transmitter (UART) protocol that is used for sending low-speed data between devices. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lxxx Freescale Semiconductor...
Page 83 FCC implementation of the transparent protocol. — Chapter 38, “Serial Peripheral Interface (SPI),” describes the serial peripheral interface, which allows the PowerQUICC II to exchange data between other PowerQUICC II chips, the MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor lxxxi...
Page 84 — Programming Environments for 32-Bit Implementations of the PowerPC Architecture, REV 2 (Freescale order #: MPCFPE32B/D) • The Programmer’s Pocket Reference Guide for the PowerPC Architecture: MPCPRGREF/D—This provides an overview of registers, instructions, and exceptions for 32-bit implementations. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lxxxii Freescale Semiconductor...
Page 85: Acronyms And Abbreviations
(such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. Table iii. Acronyms and Abbreviated Terms Term Meaning Analog-to-digital Arithmetic logic unit Asynchronous transfer mode Buffer descriptor MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor lxxxiii...
Page 86 Floating-point status and control register Floating-point unit General circuit interface GPCM General-purpose chip-select machine General-purpose register Graphical user interface HDLC High-level data link control Inter-integrated circuit Inter-chip digital link MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lxxxiv Freescale Semiconductor...
Page 87 Personal Computer Memory Card International Association Processor identification register Primary rate interface Processor version register RISC Reduced instruction set computing RTOS Real-time operating system RWITM Read with intent to modify Receive MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor lxxxv...
Page 88 User instruction set architecture User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter Universal serial bus Virtual address Virtual environment architecture Register used primarily for indicating conditions such as carries and overflows for integer operations MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lxxxvi Freescale Semiconductor...
Page 89 Equivalent to: BA, BB, BT crbA, crbB, crbD (respectively) BF, BFA crfD, crfS (respectively) RA, RB, RT, RS rA, rB, rD, rS (respectively) SIMM UIMM /, //, /// 0...0 (shaded) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor lxxxvii...
Page 90 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 lxxxviii Freescale Semiconductor...
Page 91: Intended Audience
MSR[LE] refers to the little-endian mode enable bit in the machine state register. In certain contexts, such as in a signal encoding or a bit field, indicates a don’t care. Indicates an undefined numerical value MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 92 Institute of Electrical and Electronics Engineers ISDN Integrated services digital network ITLB Instruction translation lookaside buffer Integer unit JTAG Joint Test Action Group Least recently used (cache replacement algorithm) Load/store unit Multi-channel controller MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 93 Static random access memory Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UISA User instruction set architecture User-programmable machine Virtual environment architecture MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 94 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 95: Features
– Four-way set associative – Physically addressed – LRU replacement algorithm — PowerPC architecture-compliant memory management unit (MMU) — Common on-chip processor (COP) test interface — Supports bus snooping for cache coherency MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 96 — Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-definable peripherals — Byte write enables and selectable parity generation — 32-bit address decodes with programmable bank size MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 97 – Transparent — Two serial management controllers (SMCs), identical to those of the MPC860 – Provide management for BRI devices as general-circuit interface (GCI) controllers in time- division-multiplexed (TDM) channels MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 98 – Payload descrambling using self synchronizing scrambler (programmable by the user) – Coset removing (programmable by the user) – Filtering idle/unassigned cells (programmable by the user) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 99 — Includes all of the configuration registers (which are automatically loaded from the EPROM and used to configure the PowerQUICC II) required by the PCI standard as well as message and doorbell registers MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 100: Architecture Overview
A system interface unit (SIU) • A communications processor module (CPM) Figure 1-1 shows the block diagram of the superset PowerQUICC II device. Features that are device- or silicon-specific are noted. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 101: G2 Core
The core includes 16 Kbytes of instruction cache and 16 Kbytes of data cache. It has a 64-bit split-transaction external data bus, which is connected directly to the external PowerQUICC II pins. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 102: System Interface Unit (Siu)
A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt timer, and other system functions useful in embedded applications. • Glueless interface to L2 cache (MPC2605) and 4-/16-K-entry CAM (MCM69C232/MCM69C432). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 103: Communications Processor Module (Cpm)
Although many registers are new, most registers retain the old status and event bits, so an understanding of the programming models of the MC68360, MPC860, or MPC85015 is helpful. Note that the MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 104: Signals
(active) when they are low and negated when they are high. Signals that are not active low, such as TSIZ[0–3] (transfer size signals) are referred to as asserted when they are high and negated when they are low. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 1-10 Freescale Semiconductor...
Page 105: Powerquicc Ii External Signals
NC ⎯⎯⎯> 2 1 −⎯⎯> TDO MPC8250, MPC8265, and MPC8266 only. MPC8250, MPC8265, and MPC8266 only. This is a spare pin on all other devices. Figure 1-2. PowerQUICC II External Signals MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 1-11...
Page 106: Differences Between Mpc860 And Powerquicc Ii
ATM (Utopia) √ 100BaseT √ √ 10BaseT √ √ √ HDLC √ HDLC_BUS √ √ √ √ Transparent √ √ UART √ DPLL √ Multichannel Not on the MPC8250 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 1-12 Freescale Semiconductor...
Page 107: Powerquicc Ii Configurations
166 MHz 66 MHz 100 BaseT 16 * 576 Kbps 166 MHz 66 MHz For all PowerQUICC II devices, except for the MPC8250 (see Table 1-3). Not on the MPC8255. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 1-13...
Page 108: Application Examples
Section 1.7.1.5, “Telecommunications Switch Controller” • Section 1.7.1.6, “SONET Transmission Controller” 1.7.1.1 Remote Access Server Figure 1-3 shows remote access server configuration (refer to note at the beginning of Section 1.7, “Application Examples”). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 1-14 Freescale Semiconductor...
Page 109: Remote Access Server Configuration
Data to and from the DSPs can be transferred through the parallel bus with the internal virtual IDMA. The PowerQUICC II memory controller supports many types of memories, including EDO DRAM and page-mode, pipeline SDRAM for efficient burst transfers. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 1-15...
Page 110: Regional Office Router
1.7.1.3 LAN-to-WAN Bridge Router Figure 1-5 shows a LAN-to-WAN router configuration, which is similar to the previous example (refer to note at the beginning of Section 1.7, “Application Examples”). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 1-16 Freescale Semiconductor...
Page 111: Cellular Base Station
PowerQUICC II SDRAM/DRAM/SRAM TDM0 Framer 60x Bus Channelized Data (up to 256 channels) TDM1 DSP Bank Local Bus Slow Slaves Comm SMC/I2C/SPI/SCC Local Figure 1-6. Cellular Base Station Configuration MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 1-17...
Page 112: Telecommunications Switch Controller
(higher) speed, if the application requires it. 1.7.1.6 SONET Transmission Controller Figure 1-8 shows a SONET transmission controller configuration (refer to note at the beginning of Section 1.7, “Application Examples”) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 1-18 Freescale Semiconductor...
Page 113: Bus Configurations
64-bit 60x data bus. The 32-bit local bus data is needed to store connection tables for many active ATM connections. The local bus may also be used to store data that does not need to be heavily processed by the MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 114: High-Performance Communication
Connection Tables Channels SDRAM/SRAM/DRAM/Flash 155 Mbps 60x Bus UTOPIA PowerQUICC II B (master/slave) Communication Channels SDRAM/SRAM/DRAM 155 Mbps Local Bus UTOPIA Connection Tables PCI Bus Figure 1-10. High-Performance Communication MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 1-20 Freescale Semiconductor...
Page 115: High-Performance System Microprocessor
In this system, the MPC603e core internal is disabled and an external high-performance microprocessor is connected to the 60x bus. 1.7.2.4 Figure 1-12 for PCI configuration. (Refer to note at the beginning of Section 1.7, “Application Examples.”) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 1-21...
Page 116: Pci With 155-Mbps Atm
This system supports PCI and implements a 155-Mbps, full-duplex ATM with more than 128 active connections. The PowerQUICC II cannot support both functions simultaneously. The local bus is needed MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 1-22 Freescale Semiconductor...
Page 117: Powerquicc Ii As Pci Agent
An external PCI bridge is used to connect the host to the PCI bus. The internal PCI bridge in the PowerQUICC II is used to bridge between the PCI bus and the 60x bus on the PowerQUICC II. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 118 Overview MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 1-24 Freescale Semiconductor...
Page 119: Overview
PowerPC architecture. The processor core implements the 32-bit portion of the PowerPC architecture, which supports 32-bit effective addresses. Figure 2-1 is a block diagram of the processor core. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 120: Powerquicc Ii Integrated Processor Core Block Diagram
D Cache I Cache JTAG/COP Clock Interface Multiplier Touch Load Buffer Core Interface Copy-Back Buffer 32-Bit Address Bus 32-/64-Bit Data Bus Figure 2-1. PowerQUICC II Integrated Processor Core Block Diagram MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 121: G2 Processor Core Features
• Five independent execution units and two register files — BPU featuring static branch prediction — A 32-bit IU — Fully IEEE 754-compliant FPU for both single- and double-precision operations MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 122 — On-chip cache locking options for the instruction and data caches (1–3 ways or the entire cache contents can be locked) — In-system testability and debugging features through JTAG and boundary-scan capability MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 123: Instruction Unit
The BPU uses a bit in the instruction encoding to predict the direction of the conditional branch. Therefore, when an unresolved conditional branch instruction is encountered, instructions are fetched from the predicted target stream until the conditional branch is resolved. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 124: Independent Execution Units
The LSU executes all load and store instructions and provides the data transfer interface between the GPRs, FPRs, and the cache/memory subsystem. The LSU calculates effective addresses, performs data alignment, and provides sequencing for load/store string and multiple instructions. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 125: System Register Unit (Sru)
The processor core’s MMUs support up to 4 Petabytes (2 ) of virtual memory and 4 Gbytes (2 ) of physical memory (referred to as real memory in the PowerPC architecture specification) for instructions MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 126: Cache Units
Figure 2-2 shows the complete PowerQUICC II register set and the programming environment to which each register belongs. This figure includes both the PowerPC register set and the PowerQUICC II-specific registers. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 127: Powerpc Register Set
Note that the reset value of the MSR exception prefix bit (MSR[IP]), described in the G2 Core Reference Manual, is determined by the CIP bit in the hard reset configuration word in the PowerQUICC II. This is described in Section 5.4.1, “Hard Reset Configuration Word.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 128: Powerquicc Ii Programming Model—Registers
Instruction Address External Address Breakpoint Register Register (Optional) IABR SPR 282 These implementation–specific registers may not be supported by other processors or processor cores. Figure 2-2. PowerQUICC II Programming Model—Registers MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 2-10 Freescale Semiconductor...
Page 129: Powerquicc Ii-Specific Registers
1 Allows a data parity error to cause a checkstop if MSR[ME] = 0 or a machine check exception if MSR[ME] = 1. EBA and EBD let the processor operate with memory subsystems that do not generate parity. 4–6 — Reserved MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 2-11...
Page 130 For those transactions, however, CI reflects the original state determined by address translation regardless of cache disabled status. DCE is zero at power-up. 1 The data cache is enabled. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 2-12 Freescale Semiconductor...
Page 131 Address broadcast enable 0 dcbf, dcbi, and dcbst instructions are not broadcast on the 60x bus. 1 dcbf, dcbi, and dcbst generate address-only broadcast operations on the 60x bus. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 2-13...
Page 132: Hardware Implementation-Dependent Register 1 (Hid1)
IWLCK Instruction cache way lock. Useful for locking blocks of instructions into the instruction cache for time-critical applications that require deterministic behavior. See Section 2.4.2.3, “Cache Locking.” 19–23 — Reserved MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 2-14 Freescale Semiconductor...
Page 133: Processor Version Register (Pvr)
In addition to the functionality of the MPC603e, the PowerQUICC II has additional hardware support for misaligned little-endian accesses. Except for string/multiple load and store instructions, little-endian load/store accesses not on a word boundary generate exceptions under the same circumstances as big-endian requests. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 2-15...
Page 134: Powerpc Instruction Set
— User-level cache management — Segment register manipulation — TLB management Note that this grouping of the instructions does not indicate which execution unit executes a particular instruction or group of instructions. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 2-16 Freescale Semiconductor...
Page 135: Powerquicc Ii Implementation-Specific Instruction Set
MPC603e processor. An alignment exception is taken if these instructions are not word-aligned. Cache Implementation The PowerQUICC II processor core has separate data and instruction caches. The cache implementation is described in the following sections. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 2-17...
Page 136: Powerpc Cache Model
(modified/exclusive/invalid) protocol. Each block contains eight 32-bit words. Note that the PowerPC architecture defines the term ‘block’ as the cacheable unit. For the PowerQUICC II’s processor core, the block size is equivalent to a cache line. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 2-18 Freescale Semiconductor...
Page 137: Data Cache Organization
(for example, allowing a snoop push to be enveloped by the address and data MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 138: Instruction Cache
This behavior differs from entire cache locking where nothing is placed in the cache, even if invalid entries exist in the cache. Unlocked ways of the cache behave normally. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 2-20 Freescale Semiconductor...
Page 139: Exception Model
Once the exception is processed, execution resumes at the address of the faulting instruction (or at an alternate address provided by the exception handler). When an MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 2-21...
Page 140: Powerquicc Ii Implementation-Specific Exception Model
MSR exception prefix bit (MSR[IP]), described in the G2 Core Reference Manual , is determined by the CIP bit in the hard reset configuration word. This is described in Section 5.4.1, “Hard Reset Configuration Word.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 2-22 Freescale Semiconductor...
Page 141 The processor core differs from MPC603e User’s Manual in that it initiates an alignment exception when it detects a misaligned eciwx or ecowx instruction and does not initiate an alignment exception when a little-endian access is misaligned. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 2-23...
Page 142 IABR enable bit (bit 30) is set. System 01400 A system management interrupt is caused when MSR[EE] = 1 and the SMI input management signal is asserted. interrupt Reserved 01500–02FFF — MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 2-24 Freescale Semiconductor...
Page 143: Exception Priorities
TLB hit. A TLB is a cache of the most recently used page table entries. Software is responsible for maintaining the consistency of the MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 144: Powerquicc Ii Implementation-Specific Mmu Features
Refer to the G2 Core reference Manual for more detailed information about these features and the suggested software routines for searching the page tables. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 2-26 Freescale Semiconductor...
Page 145: Instruction Timing
G2 Core reference Manual. The new latency is reflected Table 2-6. Table 2-6. Integer Divide Latency Primary Opcode Extended Opcode Mnemonic Form Unit Cycles divwu[o][.] divw[o][.] MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 2-27...
Page 146: Differences Between The Powerquicc Ii's G2 Core And The Mpc603E Microprocessor
Performance of integer divide operations has been improved in the processor core. A divide takes half the cycles to execute as described in MPC603e User’s Manual . The new latency is reflected in Table 2-6. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 2-28 Freescale Semiconductor...
Page 147 0x10010– Reserved — 20 bytes — — 0x10023 0x10024 Bus configuration register (BCR) 32 bits reset 4.3.2.1/4-26 configuration 0x10028 60x bus arbiter configuration register (PPC_ACR) 8 bits Figure 4-22 4.3.2.2/4-29 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 148 0x10120 Base register bank 4 (BR4) 32 bits 0x0000_0000 11.3.1/11-13 0x10124 Option register bank 4 (OR4) 32 bits undefined 11.3.2/11-15 0x10128 Base register bank 5 (BR5) 32 bits 0x0000_0000 11.3.1/11-13 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 149 — 0x101A0 Local bus-assigned UPM refresh timer (LURT) 8 bits 0x00 11.3.9/11-30 0x101A1 Reserved — 24 bits — — 0x101A4 Local bus-assigned SDRAM refresh timer (LSRT) 8 bits 0x00 11.3.11/11-31 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 150 Outbound FIFO queue port register (OFQPR) 32 bits 0x0000_0000 9.12.3.4.2/9-78 0x10450 Inbound message register 0 (IMR0) 32 bits undefined 9.12.1.1/9-66 0x10454 Inbound message register 1 (IMR1) 32 bits undefined 9.12.1.1/9-66 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 151 DMA 1 next descriptor address register (DMANDAR1) 32 bits 0x0000_0000 9.13.1.6.7/9-94 0x10600 DMA 2 mode register (DMAMR2) 32 bits 0x0000_0000 9.13.1.6.1/9-88 0x10604 DMA 2 status register (DMASR2) 32 bits 0x0000_0000 9.13.1.6.2/9-90 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 152 PCI error control capture register (PCI_ECCR) 32 bits 0x0000_0000 9.11.1.14/9-40 0x108D0 PCI inbound translation address register 1 (PITAR1) 32 bits 0x0000_0000 9.11.1.15/9-42 0x108D8 PCI inbound base address register 1 (PIBAR1) 32 bits 0x0000_0000 9.11.1.16/9-42 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 153 Port A data direction register (PDIRA) 32 bits 0x0000_0000 40.2.3/40-3 0x10D04 Port A pin assignment register (PPARA) 32 bits 0x0000_0000 40.2.4/40-4 0x10D08 Port A special options register (PSORA) 32 bits 0x0000_0000 40.2.5/40-4 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 154 0x10D92 Timer 2 mode register (TMR2) 16 bits 0x0000 18.2.3/18-5 0x10D94 Timer 1 reference register (TRR1) 16 bits 0x0000 18.2.4/18-6 0x10D96 Timer 2 reference register (TRR2) 16 bits 0x0000 18.2.4/18-6 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 155 IDMA 2 event register (IDSR2) 8 bits 0x00 19.8.4/19-24 0x11029 Reserved — 24 bits — — 0x1102C IDMA 2 mask register (IDMR2) 8 bits 0x00 19.8.4/19-24 0x1102D Reserved — 24 bits — — MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 156 FCC1 mask register (FCCM1) 16 bits 0x0000_0000 30.13.3/30-90 (ATM) 35.18.2/35-20 (Ethernet) 36.9/36-14 (HDLC) 0x11316 Reserved — 16 bits — — 0x11318 FCC1 status register (FCCS1) 16 bits 0x00 36.10/36-16 (HDLC) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 3-10 Freescale Semiconductor...
Page 157 (ATM) 35.18.2/35-20 (Ethernet) 36.9/36-14 (HDLC) 0x11336 Reserved — 16 bits — — 0x11338 FCC2 status register (FCCS2) 16 bits 0x00 36.10/36-16 (HDLC) 0x11339 Reserved — 24 bits — — MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 3-11...
Page 158 (ATM) 35.18.2/35-20 (Ethernet) 36.9/36-14 (HDLC) 0x11356 Reserved — 16 bits — — 0x11358 FCC3 status register (FCCS3) 16 bits 0x00 36.10/36-16 (HDLC) 0x11359– Reserved — — — 0x113FF bytes MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 3-12 Freescale Semiconductor...
Page 159 0x11446 TC3 received cells counter (TC_RCC3) 16 bits 0x0000 34.4.1.4/34-11 0x11448 TC3 mask register (TCMR3) 16 bits 0x0000 34.4.1.4/34-11 0x1144A TC3 filtered cells counter (TC_FCC3) 16 bits 0x0000 34.4.3.6/34-13 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 3-13...
Page 160 0x11492 TC5 error cells counter (TC_ECC5) 16 bits 0x0000 34.4.3.3/34-12 0x11494 Reserved — 12 bytes — — TC Layer 6 0x114A0 TC6 mode register (TCMODE6) 16 bits 0x0000 34.4.1.1/34-7 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 3-14 Freescale Semiconductor...
Page 161 TC8 corrected cells counter (TC_CCC8) 16 bits 0x0000 34.4.3.4/34-12 0x114EE TC8 idle cells counter (TC_ICC8) 16 bits 0x0000 34.4.3.5/34-12 0x114F0 TC8 transmitted cells counter (TC_TCC8) 16 bits 0x0000 34.4.3.2/34-12 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 3-15...
Page 162 Communications Processor 0x119C0 Communications processor command register (CPCR) 32 bits 0x0000_0000 14.4.1/14-13 0x119C4 CP configuration register (RCCR) 32 bits 0x0000_0000 14.3.7/14-8 0x119C8– Reserved — 14 bytes — — 0x119D5 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 3-16 Freescale Semiconductor...
Page 163 SCC1 event register (SCCE1) 16 bits 0x0000 21.19/21-19 (UART) 0x11A14 SCC1 mask register (SCCM1) 16 bits 0x0000 22.11/22-12 (HDLC) 23.14/23-15 (BISYNC) 24.12/24-11 (Transparent) 25.20/25-20 (Ethernet) 0x11A16 Reserved — 8 bits — — MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 3-17...
Page 164 SCC2 event register (SCCE2) 16 bits 0x0000 21.19/21-19 (UART) 0x11A34 SCC2 mask register (SCCM2) 16 bits 0x0000 22.11/22-12 (HDLC) 23.14/23-15 (BISYNC) 24.12/24-11 (Transparent) 25.20/25-20 (Ethernet) 0x11A36 Reserved — 8 bits — — MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 3-18 Freescale Semiconductor...
Page 165 SCC3 event register (SCCE3) 16 bits 0x0000 21.19/21-19 (UART) 0x11A54 SCC3 mask register (SCCM3) 16 bits 0x0000 22.11/22-12 (HDLC) 23.14/23-15 (BISYNC) 24.12/24-11 (Transparent) 25.20/25-20 (Ethernet) 0x11A56 Reserved — 8 bits — — MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 3-19...
Page 166 SCC4 mask register (SCCM4) 16 bits 0x0000 22.11/22-12 (HDLC) 23.14/23-15 (BISYNC) 24.12/24-11 (Transparent) 25.20/25-20 (Ethernet) 0x11A77 SCC4 status register (SCCS4) — 8 bits 0x00 21.20/21-21 (UART) 22.12/22-14 (HDLC) 23.15/23-16 (BISYNC) 24.13/24-12 (Transparent) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 3-20 Freescale Semiconductor...
Page 167 — — 0x11AFF CPM Mux 0x11B00 CPM mux SI1 clock route register (CMXSI1CR) 8 bits 0x00 16.4.2/16-12 0x11B02 CPM mux SI2 clock route register (CMXSI2CR) 8 bits 0x00 16.4.3/16-12 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 3-21...
Page 168 MCC1 mask register (MCCM1) 16 bits 0x0000 28.8.1/28-37 0x11B36 Reserved — 16 bits — — 0x11B38 MCC1 configuration register (MCCF1) 8 bits 0x00 28.6/28-33 0x11B39– Reserved — 7 bytes — — 0x11B3F MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 3-22 Freescale Semiconductor...
Page 169 0x125FF bytes 0x12600– Reserved — — — 0x127FF bytes SI2 RAM 0x12800– SI 2 transmit routing RAM (SI2TxRAM) undefined 15.4.3/15-10 0x129FF bytes 0x12A00– Reserved — — — 0x12BFF bytes MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 3-23...
Page 170 MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices. Reserved on the MPC8255. MPC8264 and MPC8266 only. Reserved on all other devices. Reserved on the MPC8250. Reserved on the MPC8250 and the MPC8255. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 3-24 Freescale Semiconductor...
Page 171 Instruction syntax used to identify a destination GPR REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor II-1...
Page 172 Institute of Electrical and Electronics Engineers Least-significant byte Least-significant bit Load/store unit Most-significant byte Most-significant bit Machine state register Peripheral component interconnect RTOS Real-time operating system Receive Special-purpose register Software watchdog timer Transmit MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 II-2 Freescale Semiconductor...
Page 173: Siu Block Diagram
Figure 4-1. SIU Block Diagram The system configuration and protection functions provide various monitors and timers, including the bus monitor, software watchdog timer, periodic interrupt timer, and time counter. The clock synthesizer MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 174: System Configuration And Protection
45-bit counter and an alarm register. A maskable interrupt is generated when the counter reaches the value programmed in the alarm register. The time counter (TMCNT) is clocked by the timersclk clock. Section 4.1.3, “Time Counter (TMCNT).” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 175: Bus Monitor
The two SIU timers (the time counter and the periodic interrupt timer) use the same clock source, timersclk, which can be derived from several sources, as described in Figure 4-3. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 176: Time Counter (Tmcnt)
It can also be programmed to generate an interrupt every second. The time counter control and status register (TMCNTSC) is used to enable or disable the various timer functions and report the interrupt source. Figure 4-4 shows a block diagram of TMCNT. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 177: Periodic Interrupt Timer (Pit)
PISCR[PS] Counter for PIT Disable Interrupt PISCR[PIE] Figure 4-5. PIT Block Diagram The time-out period is calculated as follows: PITC 1 PITC 1 ----------------------------------- - ------------------------ - period 8192 timersclk MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 178: Software Watchdog Timer
Although most software disciplines permit or even encourage the watchdog concept, some systems require a selection of time-out periods. For this reason, the software watchdog timer must provide a selectable range for the time-out period. Figure 4-7 shows how to handle this need. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 179: Interrupt Controller
• Programmable priority between SCCs, FCCs, and MCCs • Two priority schemes for the SCCs: grouped, spread • Programmable highest priority request • Unique vector number for each interrupt source MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 180: Interrupt Configuration
IDMA1 IDMA2 IDMA3 IDMA4 Notes SDMA MPC8250, MPC8265, and MPC8266 only RISC Timers Not on MPC8250 and MPC8255 TC layers MPC8264 and MPC8266 only Figure 4-8. PowerQUICC II Interrupt Structure MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 181: Machine Check Interrupt
The interrupt controller has 37 interrupt sources that assert one interrupt request to the core. Table 4-2 shows prioritization of all interrupt sources. As described in following sections, flexibility exists in the MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 182 No (TMCNT,PIT,PCI = Yes) XSIU8 (Grouped) No (TMCNT,PIT,PCI = Yes) XSIU3 (Spread) No (TMCNT,PIT,PCI = Yes) YCC1 (Grouped) YCC2 (Grouped) YCC3 (Grouped) YCC4 (Grouped) YCC5 (Grouped) YCC6 (Grouped) YCC7 (Grouped) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-10 Freescale Semiconductor...
Page 183 Parallel I/O–PC9 Parallel I/O–PC8 IRQ6 IDMA3 IRQ7 Timer 3 XSIU6 (GSIU = 1) No (TMCNT,PIT,PCI = Yes) YCC5 (Spread) Parallel I/O–PC7 Parallel I/O–PC6 Parallel I/O–PC5 Timer 4 YCC6 (Spread) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-11...
Page 184: Scc, Fcc, And Mcc Relative Priority
CPM interrupt sources. This scheme is ideal for applications where all SCCs, FCCs, and MCCs function at a very high data rate and interrupt latency is very important. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-12...
Page 185: Pit, Tmcnt, Pci, And Irq Relative Priority
Table 4-2 shows which interrupt sources have multiple interrupting events. Figure 4-9 shows an example of how the masking occurs, using an SCC as an example. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-13...
Page 186: Interrupt Vector Generation And Calculation
Table 4-3. Encoding the Interrupt Vector Interrupt Number Interrupt Source Description Interrupt Vector Error (No interrupt) 0b00_0000 0b00_0001 0b00_0010 RISC Timers 0b00_0011 SMC1 0b00_0100 SMC2 0b00_0101 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-14 Freescale Semiconductor...
Page 187 IRQ7 0b01_1001 26–31 Reserved 0b01_1010–01_1111 FCC1 0b10_0000 FCC2 0b10_0001 FCC3 0b10_0010 Reserved 0b10_0011 MCC1 0b10_0100 MCC2 0b10_0101 Reserved 0b10_0110 Reserved 0b10_0111 SCC1 0b10_1000 SCC2 0b10_1001 SCC3 0b10_1010 SCC4 0b10_1011 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-15...
Page 188: Port C External Interrupts
Each port C line asserts a unique interrupt request to the interrupt pending register and has a different internal interrupt priority level within the interrupt controller. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-16...
Page 189: Programming Model
Table 4-2. Field — — GSIU SPS Reset 0000_0000_0000_0000 Addr 0x0x10C00 Figure 4-10. SIU Interrupt Configuration Register (SICR) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-17...
Page 190: Siu Interrupt Priority Register (Siprr)
0000 Addr 0x0x10C10 Field XS5P XS6P XS7P XS8P — Reset 0000 Addr 0x10C12 Figure 4-11. SIU Interrupt Priority Register (SIPRR) The SIPRR register bits are described in Table 4-5. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-18 Freescale Semiconductor...
Page 191: Cpm Interrupt Priority Registers (Scprr_H And Scprr_L)
XC4P — Reset 0000 Addr 0x0x10C14 Field XC5P XC6P XC7P XC8P — Reset 0000 Addr 0x10C16 Figure 4-12. CPM High Interrupt Priority Register (SCPRR_H) Table 4-6 describes SCPRR_H fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-19...
Page 192: Cpm Low Interrupt Priority Register (Scprr_L)
YC4P — Reset 0000 Addr 0x0x10C18 Field YC5P YC6P YC7P YC8P — Reset 0000 Addr 0x10C20 Figure 4-13. CPM Low Interrupt Priority Register (SCPRR_L) Table 4-7 describes SCPRR_L fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-20 Freescale Semiconductor...
Page 193: Siu Interrupt Pending Registers (Sipnr_H And Sipnr_L)
These fields are zero after reset because their corresponding mask register bits are cleared (disabled). MPC8250, MPC8265, and MPC8266 only. Reserved on all other devices. Figure 4-14. SIPNR_H Figure 4-15 shows SIPNR_L fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-21...
Page 194: Siu Interrupt Mask Registers (Simr_H And Simr_L)
SIMR bit later, a previously pending interrupt request is processed by the core, according to its assigned priority. The SIMR can be read by the user at any time. Figure 4-16 shows the SIMR_H register. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-22 Freescale Semiconductor...
Page 195: Simr_H
(if no other interrupts pending). Thus, the user should always include an error vector routine, even if it contains only an rfi instruction. The error vector cannot be masked. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-23...
Page 196: Siu Interrupt Vector Register (Sivec)
256 instructions. The interrupt code is defined such that its two lsbs are zeroes, allowing indexing into the table, as shown in Figure 4-19. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-24 Freescale Semiconductor...
Page 197: Siu External Interrupt Control Register (Siexr)
C line asserts an interrupt request upon either a high-to-low change or any change on the pin. External interrupts can come from port C (PC[0-15]). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-25...
Page 198: System Configuration And Protection Registers
The system configuration and protection registers are described in the following sections. 4.3.2.1 Bus Configuration Register (BCR) The bus configuration register (BCR), shown in Figure 4-21, contains configuration bits for various features and wait states on the 60x bus. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-26 Freescale Semiconductor...
Page 199: Bus Configuration Register (Bcr)
1 The memory controller inserts one wait state between the assertion of TS and the assertion of CS when accessing an address space controlled by the memory controller. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-27...
Page 200 0 The bus master connected to the arbitration lines is a PowerQUICC II. 1 The bus master connected to the arbitration lines is not a PowerQUICC II. 19–20 — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-28 Freescale Semiconductor...
Page 201: X Bus Arbiter Configuration Register (Ppc_Acr)
DBGD EARB PRKM Reset See note 0010 Addr 0x0x10028 Depends on reset configuration sequence. See Section 5.4.1, “Hard Reset Configuration Word.” Figure 4-22. PPC_ACR Table 4-10 describes PPC_ACR fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-29...
Page 202: X Bus Arbitration-Level Registers (Ppc_Alrh/Ppc_Alrl)
0000 0001 0010 0110 Addr 0x0x1002C Field Priority Field 4 Priority Field 5 Priority Field 6 Priority Field 7 Reset 0011 0100 0101 0111 Addr 0x1002E Figure 4-23. PPC_ALRH MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-30 Freescale Semiconductor...
Page 203: Local Bus Arbiter Configuration Register (Lcl_Acr)
0 DBG is asserted with TS if the data bus is free. 1 DBG is asserted one cycle after TS if the data bus is not busy. Section 8.5.1, “Data Bus Arbitration.” — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-31...
Page 204: Local Bus Arbitration Level Registers (Lcl_Alrh And Lcl_Acrl)
Priority Field 6 Priority Field 7 Reset 0011 0100 0101 0111 Addr 0x10040 Figure 4-26. LCL_ALRH LCL_ALRL, shown in Figure 4-27, defines arbitration priority of PowerQUICC II local bus masters 8–15. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-32 Freescale Semiconductor...
Page 205: Siu Module Configuration Register (Siumcr)
1 ABB/IRQ2 pin is IRQ2, DBB/IRQ3 pin is IRQ3 External snoop enable. Configures GBL/IRQ1 0 External snooping disabled. (GBL/IRQ1 pin is IRQ1) 1 External snooping enabled. (GBL/IRQ1 pin is GBL) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-33...
Page 206 00 Local bus pins function as local bus 01 Local bus pins function as PCI bus (MPC8250, MPC8265, and MPC8266 only). Reserved on all other devices. 10 Local bus pins function as core pins 11 Reserved MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-34 Freescale Semiconductor...
Page 207 10 The PowerQUICC II’s internal core bus request masked and external bus requests two and three masked (boot master connected to external bus request 1). 11 All external bus requests masked (boot master is the PowerQUICC II’s internal core). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-35...
Page 208: Internal Memory Map Register (Immr)
0x0011 (.29µm Rev A.1); 0x0023 (.29µm Rev B.3); 0x0024 (.29µm Rev C.2); 0x0060 (.25µm Rev A.0) Addr 0x101AA Figure 4-29. Internal Memory Map Register (IMMR) Table 4-13 describes IMMR fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-36 Freescale Semiconductor...
Page 209: System Protection Control Register (Sypccr)
SYPCR can be read at any time but can be written only once after system reset. Field SWTC Reset 1111_1111_1111_1111 Addr 0x0x10004 Field PBME LBME — SWE SWRI SWP Reset 1111_1111 00_0 Addr 0x10006 Figure 4-30. System Protection Control Register (SYPCCR) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-37...
Page 210: Software Service Register (Swsr)
4.3.2.10 60x Bus Transfer Error Status and Control Register 1 (TESCR1) The 60x bus transfer error status and control register 1 (TESCR1) is shown in Figure 4-31. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-38 Freescale Semiconductor...
Page 211: X Bus Transfer Error Status And Control Register 1 (Tescr1)
Note that this alone does not cause TEA assertion. Usually, in this case, the bus monitor will time-out. External error. Indicates that TEA was asserted by an external bus slave. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-39...
Page 212: X Bus Transfer Error Status And Control Register 2 (Tescr2)
ECNT. The counter starts from this value instead of zero. 4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2) The 60x bus transfer error status and control register 2 (TESCR2) is shown in Figure 4-32. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-40 Freescale Semiconductor...
Page 213: X Bus Transfer Error Status And Control Register 2 (Tescr2)
60x bus memory controller bank that had an error. Note that this field is invalid if the error was not caused by ECC or parity checks. 28–31 — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-41...
Page 214: Local Bus Transfer Error Status And Control Register 1 (L_Tescr1)
Transfer type. Indicates the transfer type of the local bus transaction that caused the TEA. Section 8.4.3.1, “Transfer Type Signal (TT[0–4]) Encoding,” describes the various transfer types. — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-42 Freescale Semiconductor...
Page 215: Local Bus Transfer Error Status And Control Register 2 (L_Tescr2)
Note that BNK is invalid if the error was not caused by ECC or PARITY checks. 28–31 — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-43...
Page 216: Time Counter Status And Control Register (Tmcntsc)
Figure 4-36, contains the current value of the time counter. The counter is reset to zero on PORESET reset or hard reset but is not effected by soft reset. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-44 Freescale Semiconductor...
Page 217: Time Counter Alarm Register (Tmcntal)
Table 4-20. TMCNTAL Field Descriptions Bits Name Description 0–31 ALARM The alarm interrupt is generated when ALARM field matches the corresponding TMCNT bits. The resolution of the alarm is 1 second. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-45...
Page 218: Periodic Interrupt Registers
4.3.3.2 Periodic Interrupt Timer Count Register (PITC) The periodic interrupt timer count register (PITC), shown in Figure 4-39, contains the 16 bits to be loaded in a modulus counter. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-46 Freescale Semiconductor...
Page 219: Periodic Interrupt Timer Register (Pitr)
The PITR counter is not affected by reads or writes to it. Field Reset 0000_0000_0000_0000 Read Only Addr 0x0x10248 Field — Reset 0000_0000_0000_0000 Read Only Addr 0x1024A Figure 4-40. Periodic Interrupt Timer Register (PITR) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-47...
Page 220: Pci Control Registers
Figure 4-41 shows the PCI base register. Field Reset 0000_0000_0000_0000 Addr 0x101AC (PCIBR0); 0x101B0 (PCIBR1) Field — Reset 0000_0000_0000_0000 Addr 0x101AE (PCIBR0); 0x101B2 (PCIBR1) Figure 4-41. PCI Base Registers (PCIBRx) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-48 Freescale Semiconductor...
Page 221: Pci Mask Register (Pcimskx)
Some functions share pins. The actual pinout of the PowerQUICC II is shown in the hardware specifications. The control of the actual functionality used on a specific pin is shown in Table 4-26. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 4-49...
Page 222 PWE[0–7]/PSDDQM[0–7]/PBS[0–7] Controlled dynamically according to the specific memory controller PSDA10/PGPL0 machine that handles the current bus transaction. PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LBS[0–3]/LSDDQM[0–3]/LWE[0–3] LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LSDRAS/LOE LGPL3/LSDCAS LPBS/LGPL4/LUPMWAIT/LGTA LGPL5/LSDAMUX MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 4-50 Freescale Semiconductor...
Page 223: Reset Causes
The enabled checkstop event then generates an internal hard reset sequence. JTAG reset When JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is generated. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 224: Reset Actions
HRESET remains asserted for another 512 clocks and is then released. The SRESET is released three clocks later. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 225: Hreset Flow
16-cycle period is taken before testing the presence of an external (hard/soft) reset. While SRESET is asserted, internal hardware is reset but hard reset configuration does not change. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 226: Reset Status Register (Rsr)
BMRS is set and remains set until the software clears it. BMRS can be cleared by writing a 1 to it (writing zero has no effect). 0 No bus monitor reset event has occurred 1 A bus monitor reset event has occurred MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 227: Reset Mode Register (Rmr)
5-3, is memory-mapped into the SIU register map. Field — Reset 0000_0000_0000_0000 Addr 0x10C94 Field — CSRE Reset 0000_0000_0000_0000 Addr 0x10C96 Figure 5-3. Reset Mode Register (RMR) Table 5-4 describes RMR fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 228: Reset Configuration
5-5. Table 5-5. RSTCONF Connections in Multiple-PowerQUICC II Systems Configured Device RSTCONF Connection Configuration master First configuration slave Second configuration slave Third configuration slave Fourth configuration slave Fifth configuration slave MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 229 HRESET in the middle of operation causes the PowerQUICC II to return to the configuration programmed after PORESET assertion (not the default configuration represented by configuration word of all zeros). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 230: Hard Reset Configuration Word
“SIU Module Configuration Register (SIUMCR).” 10–11 DPPC Data parity pin configuration. Defines the initial value of SIUMCR[DPPC]. For more details refer Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR).” — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 231 (PCI_MODE is driven low), this field has no effect and the value for MODCK_H is loaded directly from the MODCK_H pins. Note that the value of the MODCK_H bits are derived from the dedicated PCI_MODCK_H[0:3] pins when operating in PCI mode. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 232: Hard Reset Configuration Examples
RSTCONF to GND as shown in Figure 5-6. The PowerQUICC II can access the boot EPROM. It is assumed the configuration is as defined there upon exiting hard reset. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 5-10 Freescale Semiconductor...
Page 233: Multiple Powerquicc Iis Configured From Boot Eprom
PowerQUICC II that controls the boot EPROM should be the configuration master—RSTCONF tied to GND. The RSTCONF inputs of the other PowerQUICC II devices are tied to the address bus lines, thus assigning them as configuration slaves. See Figure 5-7. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 5-11...
Page 234: Configuring Multiple Chips
In this system, the configuration master initially reads its own configuration word. It then reads other configuration words and drives them to the configuration slaves by asserting RSTCONF. As Figure 5-7 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 5-12 Freescale Semiconductor...
Page 235: Multiple Powerquicc Iis In A System With No Eprom
PORESET negation, the external hardware can configure the different devices by driving appropriate configuration words on the data bus and asserting RSTCONF for each device to strobe the data being received. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 5-13...
Page 236 Reset MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 5-14 Freescale Semiconductor...
Page 237 (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor III-1...
Page 238 (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. Table III-1. Acronyms and Abbreviated Terms Term Meaning Buffer descriptor BIST Built-in self test Basic rate interface Content-addressable memory MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 III-2 Freescale Semiconductor...
Page 239 Multiply accumulate Memory management unit Most-significant byte Most-significant bit Machine state register NMSI Nonmultiplexed serial interface Open systems interconnection Peripheral component interconnect PCMCIA Personal Computer Memory Card International Association MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor III-3...
Page 240 Special-purpose register SRAM Static random access memory Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UISA User instruction set architecture User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 III-4 Freescale Semiconductor...
Page 241: Functional Pinout
(active) when they are low and negated when they are high. Signals that are not active low, such as TSIZ[0–1] (transfer size signals) are referred to as asserted when they are high and negated when they are low. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 242: Signal Descriptions
The PowerQUICC II system bus, shown in Table 6-1, consists of all the signals that interface with the external bus. Many of these pins perform different functions, depending on how the user assigns them. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 243 As an output the PowerQUICC II asserts this pin to grant 60x data bus ownership to an external bus master. As an input the external arbiter should assert this pin to grant 60x data bus ownership to the PowerQUICC II. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 244 The core resumes instructions execution once this pin is negated. EXT_DBG2 External data bus grant 2—(Output) The PowerQUICC II asserts this pin to grant 60x data bus ownership to an external bus master. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 245 Cache set entry 0—The cache set entry outputs from the core represent the cache replacement set element for the current core transaction reloading into or writing out of the cache. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 246 Section 11.2.14, “BADDR[27:31] Signal Connections.” IRQ2 Interrupt request 2—This input is one of the eight external lines that can request (by means of the internal interrupt controller) a service routine from the core. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 247 Buffer control 1—Output signal whose function is controlling buffers on the 60x data bus. Usually used with BCTL0. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR),” for details. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 248 SDRAMs’ RAS input. PGPL2 60x bus UPM general purpose line 2—One of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 249 Local bus UPM general purpose line 0—This is one of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM. PCI_MODCK_H0 PCI MODCK_H0—In PCI mode, defines the operating mode of internal clock circuits. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 250 PCI parity—PCI parity input/output pin. Assertion of this pin indicates that odd parity is driven across PCI_AD[31-0] and PCI_C/BE[3–0] during address and data phases. Negation of PCI_PAR indicates that even parity is driven across the PCI_AD[31-0] and PCI_C/BE[3–0] during address and data phases. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 6-10 Freescale Semiconductor...
Page 251 PCI parity error—PCI data parity error input/output pin. Assertion of this pin indicates that a data parity error was detected during a PCI transfer (except for a special cycle). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 6-11...
Page 252 PowerQUICC II’s internal PCI arbiter is not used, this pin is used for the Hot Swap interface to connect to the Hot Swap LED. The Hot Swap pins are not available when the internal arbiter is used. 0 LED is off 1 LED is on MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 6-12 Freescale Semiconductor...
Page 253 PCI address/data—PCI bus address/data input/output pins. During an address phase PCI_AD[31-0] contains a physical address, during a data phase PCI_AD[31-0] contains the data bytes. In the PCI address/data bus, bit 31 is msb and bit 0 is lsb. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 6-13...
Page 254 Quiescent request— Output only. Indicates that PowerQUICC II’s internal core is about to enter its low power mode. In the PowerQUICC II this pin will be typically used for debug purposes. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 6-14...
Page 255 • When High, the PCI bridge is disabled, the PowerQUICC II operates with the Local bus. This pin has an internal pull up resistor so it defaults to Local bus operation. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 256 GNDSYN—This is a special ground of the PLL circuitry. VCCSYN1—This is the power supply of the core’s PLL circuitry. MPC8250, MPC8265, and MPC8266 only. This is a spare pin in all other devices. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 6-16 Freescale Semiconductor...
Page 257 In a single-beat transaction, the data termination signals also indicate the end of the tenure. For burst accesses or extended port-size accesses, the data termination signals apply to individual beats and indicate the end of the tenure only after the final data beat. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 258: Signal Configuration
Chapter 8, “The 60x Bus,” describes many of these signals in greater detail, both in terms of their function and how groups of signals interact. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 259: Address Bus Arbitration Signals
Negation—Occurs for at least one cycle after a qualified BG even if another transaction is pending; also negated for at least one cycle following any qualified ARTRY on the bus unless this chip asserted the ARTRY and requires to perform MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 260: Bus Grant (Bg)
The external device may still assume address bus ownership on the cycle that BG is negated if it was asserted the previous cycle with other bus grant qualifications. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 261: Address Bus Busy (Abb)
Following are the state meaning and timing comments for the TS output signal. State Meaning Asserted—Indicates that the PowerQUICC II has started a bus transaction and that the address bus and transfer attribute signals are valid. It is also an implied data MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 262: Address Transfer Signals
High Impedance— Occurs the cycle following the assertion of AACK; no precharge action performed on release. 7.2.3.1.2 Address Bus (A[0–31])—Input Following are the state meaning and timing comments for the A[0–31] input signals. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 263: Address Transfer Attribute Signals
Asserted/Negated—Specifies the data transfer size for the transaction (see Section 8.4.3.3, “TBST and TSIZ[0–3] Signals and Size of Transfer”). During graphics transfer operations, these signals form part of the Resource ID (see TBST). Timing Comments Assertion/Negation—Same as A[0–31]. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 264: Transfer Burst (Tbst)
Timing Comments Assertion/Negation—Same as A[0–31]. 7.2.4.5 Caching-Inhibited (CI)—Output The cache inhibit (CI) signal is an output signal on the PowerQUICC II. Following are the state meaning and timing comments for CI. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 265: Address Transfer Termination Signals
Assertion—Occurs a programmable number of clocks after TS or whenever ARTRY conditions are resolved. Negation—Occurs one clock after assertion. 7.2.5.1.2 Address Acknowledge (AACK)—Input Following are the state meaning and timing comments for AACK as an input signal. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 266: Address Retry (Artry)
Note that the subsequent address presented on the address bus may not be the one that generated the assertion of ARTRY. Negated/High Impedance—Indicates that the PowerQUICC II does not need to retry the last address tenure. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 7-10 Freescale Semiconductor...
Page 267: Data Bus Arbitration Signals
ARTRY signal is only for the address bus tenure associated with the data bus tenure about to be granted (that is, not for another address tenure available because of address pipelining). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 7-11...
Page 268: Data Bus Busy (Dbb)
The data bus consists of 64 signals that are both inputs and outputs on the PowerQUICC II. Following are the state meaning and timing comments for the data bus. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 7-12 Freescale Semiconductor...
Page 269: Data Bus (D[0–63])—Input
The eight data bus parity (DP[0–7]) signals both output and input signals. 7.2.7.2.1 Data Bus Parity (DP[0–7])—Output Following are the state meaning and timing comments for the DP[0–7] output signals. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 7-13...
Page 270: Data Transfer Termination Signals
Following are the state meaning and timing comments for the TA input signal. State Meaning Asserted—Indicates that a single-beat data transfer completed successfully or that a data beat in a burst transfer completed successfully. Note that TA must be MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 7-14 Freescale Semiconductor...
Page 271: Transfer Acknowledge (Ta)—Output
PCI controller can initiate global transactions—Assertion must occur at least one clock cycle following AACK for the current transaction and at least one clock cycle after ARTRY can be asserted. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 7-15...
Page 272: Transfer Error Acknowledge (Tea)
State Meaning Asserted—Indicates that a beat data transfer completed successfully. Note that PSDVAL must be asserted for each data beat in a single beat, port size and burst MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 7-16 Freescale Semiconductor...
Page 273: Partial Data Valid (Psdval)—Output
Negation—Occurs after the clock cycle of the final (or only) data beat of the transfer. For a burst transfer, PSDVAL may be negated between beats to insert one or more wait states before the completion of the next beat. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 7-17...
Page 274 60x Signals MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 7-18 Freescale Semiconductor...
Page 275: Terminology
The device that owns the address or data bus, the device that initiates or requests the transaction. Modified Identifies a cache block The M state in a MESI or MEI protocol. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 276: Bus Configuration
In single-PowerQUICC II bus mode, the PowerQUICC II is the only bus device in the system. The internal memory controller controls all devices on the external pins. Figure 8-1 shows the signal connections for single-PowerQUICC II bus mode. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 277: X-Compatible Bus Mode
The 60x-compatible bus mode can include one or more potential external masters (for example, an L2 cache, an ASIC DMA, a high-end processor that implements the PowerPC architecture, or a second PowerQUICC II). When operating in a multiprocessor configuration, the PowerQUICC II snoops bus MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 278: X Bus Protocol Overview
Figure 8-3 shows a data transfer that consists of a single-beat transfer of as many as 256 bits. Four-beat burst transfers of 32-byte cache blocks MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 279: Arbitration Phase
In the latter case, the system is optimized for three external bus masters besides the PowerQUICC II. The arbitration configuration (external or internal) is determined at MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 280: Address Pipelining And Split-Bus Transactions
These benefits are most fully realized in shared-memory, multiple-master implementations where bus bandwidth is critical to system performance. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 281: Address Tenure Operations
The series of address transfers in Figure 8-4 shows the transfer protocol when the PowerQUICC II is configured in 60x-compatible bus mode. In this example, PowerQUICC II is initially parked on the bus MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 282: Address Pipelining
The PowerQUICC II pipelines data bus operations in strict order with the associated address operations. Figure 8-5 shows how address pipelining allows address tenures to overlap the associated data tenures. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 283: Transfer Type Signal (Tt[0–4]) Encoding
The transfer type signals define the nature of the transfer requested. They indicate whether the operation is an address-only transaction or whether both address and data are to be transferred. Table 8-2 describes the PowerQUICC II’s action as master, slave, and snooper. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 284 AACK is asserted; PowerQUICC II takes no further action. 01101 icbi Address Not applicable Not applicable Not applicable Address-only only operation. AACK is asserted; PowerQUICC II takes no further action. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 8-10 Freescale Semiconductor...
Page 285 TT1 can be interpreted as a read-versus-write indicator for the bus. This column specifies the TT encoding for the general 60x protocol. The processor generates or snoops only a subset of those encodings. NOTE Regarding Table 8-2: MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 8-11...
Page 286: Transfer Code Signals Tc[0–2]
The PowerQUICC II uses four double-word burst transactions for transferring cache blocks. For these transactions, TSIZ[0–3] are encoded as 0b0010, and address bits A[27–28] determine which double-word is sent first. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 8-12 Freescale Semiconductor...
Page 287: Burst Ordering During Data Transfers
Table 8-5 describes PowerQUICC II burst ordering. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 8-13...
Page 288: Effect Of Alignment On Data Transfers
— — — 0 0 1 0 1 0 0 — — — — — — 0 0 1 0 1 1 0 — — — — — — MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 8-14 Freescale Semiconductor...
Page 289 — Misaligned—1st access 0 1 1 1 0 1 — — — — — 2nd access 0 0 1 0 0 0 — — — — — — — MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 8-15...
Page 290: Effect Of Port Size On Data Transfers
64-bit bus is assumed. Figure 8-6. shows the device connections on the data bus. Table 8-8 lists the bytes required on the data bus for read cycles. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 8-16 Freescale Semiconductor...
Page 291: Interface To Different Port Size Devices
Interface Output Register D[0–7] D[8–15] D[15–23] D[24–31] D[32–39] D[40–47] D[48–55] D[56–63] 64-Bit Port Size 32-Bit Port Size 16-Bit Port Size 8-Bit Port Size Figure 8-6. Interface to Different Port Size Devices MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 8-17...
Page 292: X-Compatible Bus Mode—Size Calculation
In 60x-compatible bus mode, the external slave or master must determine the new address and size. Table 8-9 describes the address and size MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 8-18 Freescale Semiconductor...
Page 293: Extended Transfer Mode
PowerPC architecture. The PowerQUICC II can generate 5-, 6-, 7-, MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 294 OP2 OP3 OP4 OP5 OP6 OP7 — OP2 OP3 — OP1 OP1 Table 8-12 includes added states to the transfer size calculation state machine. Only extended transfers use these states. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 8-20 Freescale Semiconductor...
Page 295 3-Byte Byte Half Half Byte Word Byte 3-Byte 5-Byte Byte Word Half 3-Byte Word Word Byte Word Double Stop 6-Byte Byte 5-Byte Half Word Word Half Word Double Stop MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 8-21...
Page 296: Address Transfer Termination
8-7. Note that after recognizing an assertion of ARTRY and aborting the current transaction, the PowerQUICC II may not run the same transaction the next time it is granted the bus. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 8-22 Freescale Semiconductor...
Page 297: Retry Cycle
(registers or cache). Generally, the memory system must also detect this event and abort any transfer in progress. If this MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 298: Address Tenure Timing Configuration
In 60x-compatible bus mode, a two-level pipeline depth can occur (for example, when an external 60x-bus slave does not support MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 8-24 Freescale Semiconductor...
Page 299: Data Tenure Operations
(by a master which was granted the bus) or in the following cycle. In case the external arbiter asserts DBG on the cycle in which TS was asserted, PPC_ACR[DBGD] should be zero. Otherwise, PPC_ACR[DBGD] should be set. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 8-25...
Page 300: Data Streaming Mode
(the data tenure may not be terminated due to address pipelining). The earliest allowable assertion of TA depends directly on the latest possible assertion of ARTRY. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 8-26 Freescale Semiconductor...
Page 301: Effect Of Artry Assertion On Data Transfer And Arbitration
The fourth assertion of PSDVAL in conjunction with TA signals the end of a burst transfer. Figure 8-9 shows an extended transaction of 4 words to a port size of 32 bits. The single-beat transaction is translated to four port-sized beats. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 8-27...
Page 302: Bit Extended Transfer To 32-Bit Port Size
32-bit port. Each double-word burst beat is divided into two port-sized beats such that the four double words are transferred in eight beats. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 8-28 Freescale Semiconductor...
Page 303: Data Bus Termination By Assertion Of Tea
This sequence is shown in Figure 8-11. In Figure 8-11 the data bus is busy at the beginning of the transaction, thus delaying the assertion of DBG. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 8-29...
Page 304: Memory Coherency—Mei Protocol
When the PowerQUICC II processor is not the address bus master, GBL is an input. The PowerQUICC II processor snoops a transaction if TS and GBL are asserted together in the same bus clock cycle (a qualified MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 8-30...
Page 305: Processor State Signals
Processor State Signals This section describes the PowerQUICC II’s support for atomic update and memory through the use of the lwarx/stwcx. instruction pair. It also describes the TLBISYNC input. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 8-31...
Page 306: Support For The Lwarx/Stwcx. Instruction Pair
(left most) byte of the double word on D[0–7]. If the processor interfaces with a true little-endian environment, the system may need to perform byte-lane swapping or other operations external to the processor. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 8-32 Freescale Semiconductor...
Page 307 Support for 66 MHz, 3.3 V specification • Uses a buffer pool for the 60x-PCI bus interface • Makes use of the local bus signals to avoid the need for additional pins MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 308: Pci Bridge In The Powerquicc Ii
Figure 9-1. PCI Bridge in the PowerQUICC II PowerQUICC II 60x Bus/Local SDMA PowerQUICC II 60x Interface Internal PCI Bridge I/O Sequencer Buffer Pool Embedded Utilities PCI Interface Regs PCI Bus Figure 9-2. PCI Bridge Structure MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 309: Clocking
No change occurs when the programmed option is the 60x bus. Refer to the descriptions of DTB and BIB in Table 30-16. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 310: Interrupts From Pci Bridge
PCI bridge is able to service. This number depends on the processor type of the master. For example, up to two second generation (G2) processors that implement the PowerPC architecture or three third generation (G3) processors can be accommodated. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 311: Compactpci Hot Swap Specification Support
Supports posting of processor to PCI and PCI to memory writes • Supports selectable snoop • PCI host bridge capabilities • PCI agent mode capabilities which include the ability to configure from a remote host MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 312: Pci Interface Operation
PCI bus commands indicate the type of transaction occurring on the bus. These commands are encoded on PCI_C/BE[3-0] during the address phase of the transaction. PCI bus commands are described in Table 9-2. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 313: Pci Protocol Fundamentals
All signals are sampled on the rising edge of the PCI clock. Each signal has a setup and hold window with respect to the rising clock edge, in which transitions are not allowed. Outside this aperture, signal values or transitions have no significance. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 314: Basic Transfer Control
On reads, if AD[1-0] is 0b10, which represents a cache line wrap, the PCI bridge linearly increments the burst order starting at the critical word, wraps at the end of the cache MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 315: Byte Enable Signals
PCI_C/BE[3-0] signals contain a bus command. The data phase consists of the actual data transfer and possible wait cycles; the byte enable signals remain actively driven from the first clock of the data phase through the end of the transaction. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 316: Single Beat Read Example
A write transaction starts when FRAME is asserted for the first time and the PCI_C/BE[3-0] signals indicate a write command. Figure 9-5 shows an example of a single beat write transaction. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-10 Freescale Semiconductor...
Page 317: Transaction Termination
DEVSEL has remained negated for more than four clocks after the assertion of FRAME, it negates FRAME and then, on the next clock, negates IRDY. On aborted reads, the PCI bridge returns 0xFFFF_FFFF. The data is lost on aborted writes. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-11...
Page 318: Target-Initiated Terminations
PCI bus again. The PCI bridge terminates a transaction in the following cases: • Eight PCI clock cycles have elapsed between data phases. This is a ‘latency disconnect’ (see Figure 9-7). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-12 Freescale Semiconductor...
Page 319: Other Bus Operations
As a target, the PCI bridge drives DEVSEL one clock following the address phase as indicated in the configuration space status register; see Section 9.11.2.4, “PCI Bus Status Register.” The PCI bridge as a MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-13...
Page 320: Fast Back-To-Back Transactions
A disconnect occurs if the PCI bridge runs out of buffer space on writes, or the PCI bridge cannot supply consecutive data beats for reads within eight PCI bus clocks of each other. A disconnect also occurs if the transaction crosses a 4K page boundary. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-14 Freescale Semiconductor...
Page 321: Host Mode Configuration Access
Bits 7 through 2 are also copied onto the PCI bus. The PCI bridge implements address stepping on configuration cycles so that the target’s IDSEL, which is connected directly to one of MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 322: Agent Mode Configuration Access
PCI bridge can insert wait states, but because no specific target is addressed, the message and data are valid on the first clock IRDY is asserted. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-16 Freescale Semiconductor...
Page 323: Interrupt Acknowledge
(IRDY and TRDY asserted) involving the PCI bridge. When an address or data parity error is detected, the detected-parity-error bit in the configuration space status register is set (see Section 9.11.2.4, “PCI Bus Status Register”). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-17...
Page 324: Error Reporting
PCI bridge could detect an address parity error and assert SERR or where the PCI bridge, acting as an initiator, checks for the assertion of SERR signaled by the target detecting an address parity error. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-18...
Page 325: Pci Bus Arbitration
PCI bridge itself positioned before device 0. GNTx is asserted for device x as soon as the previously granted device begins a transaction. Conceptually, the lowest priority device at any given time MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 326: Master Latency Timer
Register”) to prevent the itself from monopolizing the bus. When the master latency timer expires, the PCI bridge checks the state of its GNT signals. If the GNT signal is not asserted, the PCI bridge MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-20...
Page 327: Address Map
PCI bridge internal register logic or forwarded to the core side of the PCI bridge to be handled by the PowerQUICC II internal register logic as appropriate. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 328: Address Decode Flow Chart For Pci Mastered Transactions
60x bus Hit PCI internal registers (1): IMMR+0x10400 ≤ addr ≤ IMMR+0x10bff Execute register access to PCI interface internal registers Figure 9-12. Address Decode Flow Chart for PCI Mastered Transactions MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-22 Freescale Semiconductor...
Page 329 9-14. Note that the translation mechanism shown is an example only; the address translation, as well as the memory and I/O destinations, can be programmed independently for each address translation window. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-23...
Page 330: Address Map Programming
The address translation registers allow the remapping of inbound and outbound transactions. The reset configuration for outbound transactions are that all outbound requests from the core side of the PCI bridge MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-24...
Page 331: Pci Inbound Translation
The reset configuration for the windows is disabled; that is, after reset, the PCI bridge does not acknowledge externally mastered transactions on the PCI bus by asserting DEVSEL until the inbound translation windows are enabled. The inbound translation is performed in the PCI interface. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-25...
Page 332: Pci Outbound Translation
PCI-specific registers that detect accesses from the 60x bus side to the PCI bridge (other than PCI internal registers accesses). Refer to Section 4.3.4, “PCI Control Registers.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-26 Freescale Semiconductor...
Page 333: Configuration Registers
Inbound FIFO queue port register (IFQPR) 0x0000_0000 9.12.3.4.1/9-77 0x10444 Outbound FIFO queue port register (OFQPR) 0x0000_0000 9.12.3.4.2/9-78 0x10450 Inbound message register 0 (IMR0) undefined 9.12.1.1/9-66 0x10454 Inbound message register 1 (IMR1) undefined 9.12.1.1/9-66 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-27...
Page 334 DMA 1 byte count register (DMABCR1) 0x0000_0000 9.13.1.6.6/9-93 0x105A4 DMA 1 next descriptor address register (DMANDAR1) 0x0000_0000 9.13.1.6.7/9-94 0x10600 DMA 2 mode register (DMAMR2) 0x0000_0000 9.13.1.6.1/9-88 0x10604 DMA 2 status register (DMASR2) 0x0000_0000 9.13.1.6.2/9-90 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-28 Freescale Semiconductor...
Page 335 0x108A0 PCI error control capture register (PCI_ECCR) 0x0000_0000 9.11.1.14/9-40 0x108D0 PCI inbound translation address register 1 (PITAR1) 0x0000_0000 9.11.1.15/9-42 0x108D8 PCI inbound base address register 1 (PIBAR1) 0x0000_0000 9.11.1.16/9-42 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-29...
Page 336: Dma Controller Registers
0x10802 (POTAR0); 0x1081A (POTAR1); 0x10832 (POTAR2) Field Reset 0000_0000_0000_0000 Addr 0x10800 (POTAR0); 0x10818 (POTAR1); 0x10830 (POTAR2) Figure 9-17. PCI Outbound Translation Address Registers (POTAR x) Table 9-4. describes POTARx. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-30 Freescale Semiconductor...
Page 337: Pci Outbound Base Address Registers (Pobarx)
(without translation) to the 60x bus (see Figure 9-13). 9.11.1.5 PCI Outbound Comparison Mask Registers (POCMR x ) The PCI outbound comparison mask registers (POCMRx), shown in Figure 9-19, defines the window size to translate. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-31...
Page 338: Discard Timer Control Register (Ptcr)
Discard Timer Control Register (PTCR) The discard timer control register (PTCR), shown in Figure 9-20, configures the discard timer used to put a time limit on delayed read transactions from non-prefetchable memory. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-32 Freescale Semiconductor...
Page 339: General Purpose Control Register (Gpcr)
9.11.1.7 General Purpose Control Register (GPCR) The general purpose control register (GPCR), shown in Figure 9-21, contains control bits for rerouting interrupts and adjusting the DMA controller’s 60x bandwidth. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-33...
Page 340: General Purpose Control Register (Gpcr)
0 Machine check interrupts are not rerouted to the PCI. Sent to the core if it is enabled or output on IRQ0 if the core is disabled 1 All machine check interrupts are rerouted to PICE’s INTA. Useful in agent mode. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-34 Freescale Semiconductor...
Page 341: Pci General Control Register (Pci_Gcr)
9-23, contains status bits for various types of error conditions captured by the PCI bridge. Each status bit is set when the corresponding error condition is captured. Each bit is cleared by writing a one. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-35...
Page 342: Error Status Register (Esr)
I2O outbound free queue overflow. PCI_PERR_WR PCI parity error received on a write. PCI_PERR_RD PCI parity error received on a read. PCI_SERR PCI SERR received. PCI_TAR_ABT PCI target abort MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-36 Freescale Semiconductor...
Page 343: Error Mask Register (Emr)
0 Machine check is not enabled 1 Machine check is enabled General error/interrupt indication. Illegal register access with incorrect size. I2O_IPQO I2O inbound post queue overflow. I2O_OFQO I2O outbound free queue overflow. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-37...
Page 344: Error Control Register (Ecr)
I2O_ I2O_ PERR_ PERR_ TAR_ ADDR_ SERR PAR_ PAR_ Field — DBMC IPQO OFQO Reset 0000_0000_1111_1111 Addr 0x1088C Figure 9-25. Error Control Register (ECR) Table 9-12 describes ECR fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-38 Freescale Semiconductor...
Page 345: Pci Error Address Capture Register (Pci_Eacr)
PCI error captured. Field PCI_EAR Reset 0000_0000_0000_0000 Addr 0x10892 Field PCI_EAR Reset 0000_0000_0000_0000 Addr 0x10890 Figure 9-26. PCI Error Address Capture Register (PCI_EACR) Table 9-13. describes PCI_EACR fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-39...
Page 346: Pci Error Data Capture Register (Pci_Edcr)
The data associated with the first error captured. 9.11.1.14 PCI Error Control Capture Register (PCI_ECCR) The PCI error control capture register (PCI_ECCR), shown in Figure 9-28, stores information associated with the first PCI error captured. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-40 Freescale Semiconductor...
Page 347: Pci Error Control Capture Register (Pci_Eccr)
0001 60x master 0101 DMA All others are reserved. 15–12 Command PCI command 11–8 — Reserved, should be cleared. 7–4 Byte enables PCI byte enables. 3–2 — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-41...
Page 348: Pci Inbound Translation Address Registers (Pitarx)
PCI memory space) of the windows to be translated. These registers are tied to the GPLABARx registers; Section 9.11.2.14, “General Purpose Local Access Base Address Registers (GPLABARx).” A change MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-42 Freescale Semiconductor...
Page 349: Pci Inbound Comparison Mask Registers (Picmrx)
Register”) can be cleared to enable the host to configure the device. Some of the fields of this registers are tied to the GPLABARx registers; see Section 9.11.2.14, “General Purpose Local Access Base Address Registers (GPLABARx).” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-43...
Page 350: Pci Inbound Comparison Mask Registers (Picmrx)
The mask is 20 bits (physical address bits 31-12) which corresponds to a 4Kbyte window size. This is the smallest window size allowed. PICMR = 0b1xxx_xxxx_xxxx_1111_1111_1111_0000_0000 The mask is 12 bits (physical address bits 31-20) which corresponds to a 1Mbyte window size. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-44 Freescale Semiconductor...
Page 351: Pci Bridge Configuration Registers
Sub system vendor ID 0x0000 9.11.2.15/9-55 Sub system device ID 0x0000 9.11.2.16/9-56 Reserved — — — Capabilities pointer 0x48 9.11.2.17/9-56 Reserved — — — Interrupt line 0x00 9.11.2.18/9-56 Interrupt pin 0x01 9.11.2.19/9-57 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-45...
Page 352: Vendor Id Register
PCI bus through the PCI configuration transaction when the PCI bridge is in agent mode. The following sections describe the individual PCI configuration registers. 9.11.2.1 Vendor ID Register Figure 9-33 Table 9-20 describe the vendor ID register. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-46 Freescale Semiconductor...
Page 353: Device Id Register
PCI bus command register that provides control over the ability to generate and respond to PCI cycles. Field — FB-B SERR — PERRR — Reset 0000_0000_0000_0000 Addr 0x04 Figure 9-35. PCI Bus Command Register MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-47...
Page 354: Pci Bus Status Register
A bit is cleared whenever the register is written, and the data in the corresponding bit location is set. For example, to clear bit 14 and not affect any other bits in the register, write the value 0b0100_0000_0000_0000 to the register. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-48 Freescale Semiconductor...
Page 355: Revision Id Register
Hardwired to 1, indicating that the PCI bridge implements new capabilities on the PCI bus. 3–0 — Reserved, should be cleared. 9.11.2.5 Revision ID Register Figure 9-37 Table 9-24 describe the revision ID register. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-49...
Page 356: Pci Bus Programming Interface Register
0x01 When the PCI bridge is configured as a peripheral device to indicate the programming model supports the I O interface. 9.11.2.7 Subclass Code Register Figure 9-39 Table 9-26 describe the subclass code register. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-50 Freescale Semiconductor...
Page 357: Pci Bus Base Class Code Register
The user should note that the I O support is not fully standard compliant. 9.11.2.9 PCI Bus Cache Line Size Register Figure 9-41 Table 9-28 describe the PCI bus cache line size register. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-51...
Page 358: Pci Bus Latency Timer Register
Read-only least-significant bits of the latency timer. (The latency timer value is programmed in multiples of eight.) 9.11.2.11 Header Type Register Figure 9-43 Table 9-30 describe the header type register. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-52 Freescale Semiconductor...
Page 359: Bist Control Register
PowerQUICC II’s internal memory-mapped registers. Transactions from PCI that “hit” the PIMMRBAR are translated to the IMMR and sent to the logic that controls the internal memory-mapped registers. PIMMRBAR is shown in Figure 9-45. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-53...
Page 360: General Purpose Local Access Base Address Registers (Gplabarx)
(PICMRx)”). A write to GPLABARx causes a write to PIBARx but only to the bits allowed by the PICMRx mask. Similarly, a write to PIBARx causes a write to GPLABARx of the non-masked bits of the base address. GPLABARx is shown in Figure 9-46. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-54 Freescale Semiconductor...
Page 361: Subsystem Vendor Id Register
Memory space indicator Address is mapped to memory space (hardwired to 0). 9.11.2.15 Subsystem Vendor ID Register Figure 9-47 Table 9-34 describe the subsystem vendor ID register. Field SVID Reset 0000_0000_0000_0000 Addr 0x2C Figure 9-47. Subsystem Vendor ID Register MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-55...
Page 362: Subsystem Device Id Register
Specifies the byte offset in the configuration space containing the first item in the capabilities list. 9.11.2.18 PCI Bus Interrupt Line Register Figure 9-50 Table 9-37 describes the PCI bus interrupt line register. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-56 Freescale Semiconductor...
Page 363: Pci Bus Interrupt Pin Register
9.11.2.20 PCI Bus MIN GNT Figure 9-52 Table 9-39 describes the PCI bus MIN GNT register. Field MIN GNT Reset 0000_0000 Addr 0x3E Figure 9-52. PCI Bus MIN GNT MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-57...
Page 364: Pci Bus Max Lat
9-54, is used to determine the configuration of the PCI bus interface. TRGT_ MSTR_ Field — CFG_LOCK — PCI_HA LATENCY_DIS LATENCY_DIS Reset 0000_0000_0010_0000 Addr 0x44 Figure 9-54. PCI Bus Function Register Table 9-41. describes PCI bus function register fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-58 Freescale Semiconductor...
Page 365: Pci Bus Arbiter Configuration Register
— ARB_DIS BRIDGE MP Reset 000_0000_0000_0000 Addr 0x46 Reset value determined by PIC_CFG[1] pin value after hard reset. Refer to Table 9-42. Figure 9-55. PCI Bus Arbiter Configuration Register MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-59...
Page 366: Pci Hot Swap Register Block
Control Status Register.”) Reset 0000_0000_0000_0000 Addr 0x4A Field NXT_PTR CAP_ID Reset 0000_0000_0000_0110 Addr 0x48 Figure 9-56. Hot Swap Register Block Table 9-43 describes the Hot Swap register block fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-60 Freescale Semiconductor...
Page 367: Pci Hot Swap Control Status Register
LED on/off when the hardware is in state H2. Read/write-able. 0 LED off 1 LED on — Reserved. Should be cleared. ENUM signal mask. Read/write-able. 0 Enable signal 1 Mask signal — Reserved. Should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-61...
Page 368: Pci Configuration Register Access From The Core
PCI_CFG_DATA should match the byte-wise offset of the register being accessed. For instance, if 0x0D is the offset of the register being accessed, then the address used to access PCI_CFG_DATA must be IMMR+0x10905. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-62 Freescale Semiconductor...
Page 369: Additional Information On Endianess
PowerPC Architecture). 3.The last three bits of 0x04710500 is 0b000. 4.XOR 0b000 with 0b100 (0b000 ⊕ 0b100 = 0b100). 5.Therefore, the munged address of this register would be 0x04710504. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-63...
Page 370: Initializing The Pci Configuration Registers
SIZE field and according to big-endian byte ordering. Note that the data structure description assumes the following: • Addresses refer to 60x bus addresses. • Address and data byte ordering are big-endian. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-64 Freescale Semiconductor...
Page 371: Message Registers
The PCI bridge contains two inbound message registers and two outbound message registers. The registers are each 32 bits. The inbound registers allow a remote host or PCI master to write a 32-bit value which in MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 372: Inbound Message Registers (Imrx)
Outbound Message Registers (OMR x ) The outbound message registers, described in Figure 9-61 Figure 9-47, are accessible from the PCI bus and the 60x bus in both host and agent modes. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-66 Freescale Semiconductor...
Page 373: Door Bell Registers
PCI bus. 9.12.2.1 Outbound Doorbell Register (ODR) ODR, described in Figure 9-62 Table 9-48, is accessible from the PCI bus and the 60x bus in both host and agent modes. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-67...
Page 374: Inbound Doorbell Register (Idr)
9-49, is accessible from the PCI bus and the 60x bus in both host and agent modes. Field IMC IDR x Reset 0000_0000_0000_0000 Addr 0x1046A Field IDR x Reset 0000_0000_0000_0000 Addr 0x10468 Figure 9-63. Inbound Doorbell Register (IDR) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-68 Freescale Semiconductor...
Page 375 MFAs (Free_LIST FIFO). The other FIFO keeps track of the MFAs which have posted messages (Post_LIST FIFO). Figure 9-64 shows an example of the message queues, although there is no specific order that these queues must follow. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-69...
Page 376: Pci Configuration Identification
Inbound FIFOs The inbound FIFO allows external PCI masters to post messages to the local processor. I O defines two inbound FIFOs—an inbound post FIFO and an inbound free FIFO. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-70 Freescale Semiconductor...
Page 377: Inbound Free_Fifo Head Pointer Register (Ifhpr) And Inbound Free_Fifo Tail Pointer Register (Iftpr)
Free MFAs are picked up by the PCI masters that are pointed to by the inbound free_FIFO tail pointer, described in Figure 9-66 Table 9-51. The PCI read is performed at the inbound queue port. Hardware automatically advances this register after every read. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-71...
Page 378: Inbound Post_Fifo Head Pointer Register (Iphpr) And Inbound Post_Fifo Tail Pointer Register (Iptpr)
Figure 9-67 Table 9-52. The PCI writes are addressed to the inbound queue port. Hardware (in the I O module) automatically advances the IPHPR after every write. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-72 Freescale Semiconductor...
Page 379: Inbound Post_Fifo Head Pointer Register (Iphpr)
9-53. The local processor is responsible for updating this register. Field IPTP Reset 0000_0000_0000_0000 Addr 0x104BA Field IPTP — Reset 0000_0000_0000_0000 Addr 0x104B8 Figure 9-68. Inbound Post_FIFO Tail Pointer Register (IPTPR) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-73...
Page 380: Outbound Fifos
O hardware automatically advances the address, (i.e. OFHPR) after every write. Field OFHP Reset 0000_0000_0000_0000 Addr 0x104C2 Field OFHP — Reset 0000_0000_0000_0000 Addr 0x104C0 Figure 9-69. Outbound Free_FIFO Head Pointer Register (OFHPR) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-74 Freescale Semiconductor...
Page 381: Outbound Post_Fifo Head Pointer Register (Ophpr) And Outbound Post_Fifo Tail Pointer Register (Optpr)
The outbound post queue interrupt bit is set in the outbound interrupt status register. The status bit is cleared when the head and tail pointers are equal. The interrupt can be masked using the outbound interrupt mask register. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-75...
Page 382: Outbound Post_Fifo Head Pointer Register (Ophpr)
Posted MFAs are picked up by PCI hosts that are pointed to by the outbound post_FIFO tail pointer register, described in Figure 9-72 Table 9-57. The PCI read is performed at the outbound queue port. Hardware automatically advances this register after every read. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-76 Freescale Semiconductor...
Page 383: Inbound Fifo Queue Port Register (Ifqpr)
IFQPR should be accessed only from the PCI bus. IFQPR is described in Figure 9-73 Table 9-58. Field IFQP Reset 0000_0000_0000_0000 Addr 0x10442 Field IFQP Reset 0000_0000_0000_0000 Addr 0x10440 Figure 9-73. Inbound FIFO Queue Port Register (IFQPR) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-77...
Page 384: Outbound Fifo Queue Port Register (Ofqpr)
OMR0 or OMR1. OMISR should be accessed only from the PCI bus IFQPR should be accessed only from the PCI bus. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-78 Freescale Semiconductor...
Page 385: Outbound Message Interrupt Mask Register (Omimr)
OMIMR contains the interrupt mask of the I O, door bell, and message register events generated by the local processor. OMIMR should be accessed only from the PCI bus. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-79...
Page 386: Inbound Message Interrupt Status Register (Imisr)
The events are generated by the PCI masters. IMISR should be accessed only from the 60x bus and only in agent mode. Accesses while in host mode or from the PCI bus have undefined results. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-80 Freescale Semiconductor...
Page 387: Inbound Message Interrupt Status Register (Imisr)
Inbound message 1 interrupt. When set indicates that there is an Inbound to clear message 1 interrupt. IM0I R/Write 1 Inbound message 0 interrupt. When set indicates that there is an Inbound to clear message 0 interrupt. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-81...
Page 388: Inbound Message Interrupt Mask Register (Imimr)
0 Machine check interrupt from the inbound doorbell register is allowed. 1 Machine check interrupt is masked. IDIM Inbound doorbell interrupt mask 0 Inbound doorbell interrupt is allowed. 1 Inbound doorbell interrupt is masked. — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-82 Freescale Semiconductor...
Page 389: Messaging Unit Control Register (Mucr)
Addr 0x104E4 Figure 9-79. Messaging Unit Control Register (MUCR) Table 9-64 describes MUCR fields. Table 9-64. MUCR Field Descriptions Bits Name Access Description 31–6 — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-83...
Page 390: Queue Base Address Register (Qbar)
Name Access Description 31–20 Queue base address. Base address of circular queue in local memory. It must be aligned to a 1Mbyte boundary. 19–0 — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-84 Freescale Semiconductor...
Page 391: Dma Controller
The DMA controller supports unaligned transfers for both the source and destination addresses. It gathers data beginning at the source address and aligns the data accordingly before sending it to the destination MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 392: Dma Direct Mode
Initialize the CTM (channel transfer mode) bit in the mode register to indicate chaining mode. Other control parameters in the mode register can also be initialized here if necessary. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-86 Freescale Semiconductor...
Page 393: Dma Coherency
DMA queue. Once sufficient data is stored in the queue, a 60x memory write is initiated. The DMA controller stops the transfer either for an error condition on the PCI bus or MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 394: Dma Registers
EOTIE — TEM CTM Reset 0000_0000_0000_0000 Addr 0x10500 (DMAMR0); 0x10580 (DMAMR1); 0x10600 (DMAMR2); 0x10680 (DMAMR3) Figure 9-82. DMA Mode Register [0–3] (DMAMR x ) Table 9-66 describes DMAMRx fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-88 Freescale Semiconductor...
Page 395 PCI read command. Indicates the types of PCI read command to use. 00 PCI read 01 PCI read line 10 PCI read multiple 11 Reserved 9–8 — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-89...
Page 396: Dma Status Register [0–3] (Dmasrx)
Field — — EOSI EOCDI Reset 0000_0000_0000_0000 Addr 0x10504 (DMASR0); 0x10584(DMASR1); 0x10604 (DMASR2); 0x10684 (DMASR3) Figure 9-83. DMA Status Register [0–3] (DMASR x ) Table 9-67 describes DMASRx fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-90 Freescale Semiconductor...
Page 397: Dma Current Descriptor Address Register [0–3] (Dmacdarx)
SNEN EOSIE — Reset 0000_0000_0000_0000 Addr 0x10508 (DMACDR0); 0x10588 (DMACDR1); 0x10608 (DMACDR2); 0x10688 (DMACDR3) Figure 9-84. DMA Current Descriptor Address Register [0–3] (DMACDAR x ) Table 9-68 describes DMACDARx fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-91...
Page 398: Dma Source Address Register [0–3] (Dmasarx)
9-86, indicates the address where the DMA controller will be writing data to. This address can be in either PCI memory or 60x memory. The software has to ensure that this is a valid memory address. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-92 Freescale Semiconductor...
Page 399: Dma Byte Count Register [0–3] (Dmabcrx)
0x10522 (DMABCR0); 0x105A2(DMABCR1); 0x10622 (DMABCR2); 0x106A2 (DMABCR3) Field Reset 0000_0000_0000_0000 Addr 0x10520 (DMABCR0); 0x105A0 (DMABCR1); 0x10620 (DMABCR2); 0x106A0 (DMABCR3) Figure 9-87. DMA Byte Count Register [0–3] (DMABCR x ) Table 9-71 describes DMABCRx fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-93...
Page 400: Dma Next Descriptor Address Register [0–3] (Dmandarx)
DMA transfer. 2–1 — Reserved, should be cleared. EOTD End-of-transfer descriptor. When set indicates that this descriptor is the last one to be executed. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-94 Freescale Semiconductor...
Page 401: Dma Segment Descriptors
For each descriptor in the chain, the DMA controller starts a new DMA transfer with the control parameters specified by the descriptor. The DMA controller traverses the descriptor chain until reaching the last descriptor (with its EOTD bit set). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-95...
Page 402: Descriptor In Big Endian Mode
/* 0x8765432101234567 double word */ double d; /* 0x0123456789abcdef double word */ } Descriptor; Results: Source Address = 0x44332211 <MSB..LSB> Destination Address = 0x88776655 <MSB..LSB> Next Descriptor Address = 0x21436587 <MSB..LSB> MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-96 Freescale Semiconductor...
Page 403: Descriptor In Little Endian Mode
9.14.1.1 PCI Bus Error Signals The PCI bridge uses two error signals to interact with the PCI bus, SERR and PERR. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-97...
Page 404: Error Reporting
PCI error address capture register (PCI_EACR), the PCI data capture register (PCI_EDCR) and the PCI error control capture register. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-98 Freescale Semiconductor...
Page 405: Address Parity Error
PCI slot is populated or empty. The software still needs to mask the PCI_NO_RSP bit in the error mask register (refer to Section 9.11.1.10, “Error Mask Register (EMR)”). Any other type of transaction that is terminated with a master-abort results in a machine check interrupt. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 9-99...
Page 406: Target-Abort Error
If an external PCI master writes the inbound doorbell register such that the most significant bit is set, then bit 12 of ESR (refer to Section 9.11.1.9, “Error Status Register (ESR)”) is set and a machine check is asserted to the local processor. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 9-100 Freescale Semiconductor...
Page 407: Clock Unit
The input clock source to the PLL is an external clock oscillator at the bus frequency. The PLL skew elimination between the CLOCKIN pin and the internal bus clock is guaranteed. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 408: Main Pll
CLKIN. Ranging between 1 and 4,096, the PLL multiplication factor is held in the system clock mode register (SCMR[PLLMF]). Also, when the PLL is operating, its MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 10-2...
Page 409: Skew Elimination
DLL logic to minimize clock skew between the internal and external clocks. NOTE All PCI timings are measured relative to CLKIN1; all 60x bus timings are measured relative to CLKIN2. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 10-3...
Page 410: Pci Bridge As A Host And Generating The Pci System Clock
PCI Interface pci_clk Divider bus_clk 60x Circuit dllout PCI Circuit pci_clk clkin2 clkin1 60x Bus Clock PCI Clock Figure 10-3. PCI Bridge as a Host, Generating the PCI System Clock MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 10-4 Freescale Semiconductor...
Page 411: Cpm Clock And Pci Frequency Equations
BUS_CLK and BUS_CLK_90 are supplied to the 60x bus and to the core. • Many modules use both clocks (SIU, serials) • The external clock, CLKIN, is the same as BUS_CLK MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 10-5...
Page 412: Pll Pins
The user should also bypass GNDSYN to VCCSYN with a 0.01-µF capacitor as close as possible to the chip package. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 10-6 Freescale Semiconductor...
Page 413: Pll Filtering Circuit
MF x 580 -100 Figure 10-4 shows the filtering circuit for VCCSYN and VCCSYN1, described in Table 10-1. VCCSYN 10 Ω 10 µF 0.1 µF Figure 10-4. PLL Filtering Circuit MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 10-7...
Page 414: System Clock Control Register (Sccr)
1 Enabled Reflects the inverted value of the PCI_Mode pin. PCI_MODCK PCI_MODC Unaffected Reflects the value of the PCI_MODCK pin. 25–28 PCIDF Configuratio Unaffected PCI division factor. n pins MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 10-8 Freescale Semiconductor...
Page 415: System Clock Mode Register (Scmr)
Addr 0x10C8A Figure 10-6. System Clock Mode Register (SCMR) Table 10-3 describes SCMR fields. Also, refer to Figure 10-1 to see these fields in the system PLL block diagram. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 10-9...
Page 416: Relationships Of Scmr Parameters
(PLLDF + 1) – 1 CLKIN × BUSDF = (PLLMF + 1) – 1 (PLLDF + 1) Figure 10-7. Relationships of SCMR Parameters SCMR[CORECNF] bit values are shown in Table 10-4. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 10-10 Freescale Semiconductor...
Page 417: Basic Power Structure
The VCCSYN value is equal to the internal supply. For more information, refer to Section 1.2, “Electrical and Thermal Characteristics,” in the hardware specifications document available at wwww.freescale.com. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 10-11...
Page 418 — When stop mode is exited, the SRESET input must be asserted to the chip, the clock block resumes clocks to all blocks and then releases the reset to the whole chip. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 10-12...
Page 419: Chapter 11 Memory Controller
The memory controller supports ECC data check and correction. • Two data buffer controls (one for the local bus). • ECC/parity byte select pin, which enables a fast, glueless connection to ECC/RMW-parity devices. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-1...
Page 420: Dual-Bus Architecture
Local Memory Memory Controller Control Signals Devices CPM/Local SDRAM Master Local Address LA[14–31] Bus Interface Local Address [0–31] Local Data LD[0–31] Local Data [0–63] Bus Interface Figure 11-1. Dual-Bus Architecture MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-2 Freescale Semiconductor...
Page 421: Features
— Each machine can be assigned to the 60x or local bus. — Programmable-array-based machine controls external signal timing with a granularity of up to one quarter of an external bus clock period MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-3...
Page 422: Basic Architecture
When a memory address matches BRx[BA], the corresponding machine takes ownership of the external signals that control access and maintains control until the cycle ends. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-4 Freescale Semiconductor...
Page 423: Memory Controller Machine Selection
11-3, CS0 is used with the 16-bit boot EPROM with BR0[MS] defaulting to select the GPCM. CS1 is used as the RAS signal for 64-bit DRAM with BR1[MS] configured to select UPMA. BS[0–7] are used as CAS signals on the DRAM. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-5...
Page 424: Simple System Configuration
At every clock cycle, the logical value of the external signals specified in the RAM array is output on the corresponding UPM pins. Figure 11-4 shows a basic configuration. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-6 Freescale Semiconductor...
Page 425: Address And Address Space Checking
SDRAM machine stores its address in a page register. The page information, which the user writes to the ORx register, is used along with the bank size to compare page bits of the address to the page MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 426: Parity Generation And Checking
The core or an external master attempts a burst access to the local bus address space • A bus monitor timeout 11.2.6 Machine Check Interrupt (MCP) Generation The memory controller asserts machine check interrupt (MCP) in the following cases: • A parity error MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-8 Freescale Semiconductor...
Page 427: Data Buffer Controls (Bctlx And Lwr)
In such systems, the user should set the data pipelining bit, BRx[DR]. This creates data pipelining of one stage within the memory controller in which the data check calculations are done, thus eliminating the additional data setup time requirement. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-9...
Page 428: External Memory Controller Support
AND of the eight byte selects, allowing glueless, faster connection to ECC/RMW-parity devices. This option is enabled by setting SIUMCR[PBSE], as described in Section 4.3.2.6, “SIU Module Configuration Register (SIUMCR).” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-10 Freescale Semiconductor...
Page 429: Partial Data Valid Indication (Psdval)
PSDVAL Internal Data Bus Upper 4 bytes (32 msb) Internal Data Bus Lower 4 bytes (32 lsb) Figure 11-5. Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-11...
Page 430: Baddr[27:31] Signal Connections
LSRT Local bus assigned SDRAM refresh timer Section 11.3.11 TESCRx 60x bus error status and control registers Section 11.3.13 LTESCRx Local bus error status and control regs Section 11.3.14 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-12 Freescale Semiconductor...
Page 431: Base Registers (Brx)
Section 11.2.3, “Error Checking and Correction (ECC),” and Section 11.2.4, “Parity Generation Checking.” 00 Data errors checking disabled 01 Normal parity checking 10 Read-modify-write parity checking 11 ECC correction and checking MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-13...
Page 432 SDRAM controller must be invalidated by doing the following: 1. Disable the SDRAM refresh service by clearing PSDMR/LSDMR[RFEN]. 2. Wait at least 100 60x-bus clock cycles. 3. Clear BR x [V]. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-14 Freescale Semiconductor...
Page 433: Option Registers (Orx)
Reset values are for OR0 only. OR1–11 undefined at reset. Figure 11-7. Option Registers (OR x )—SDRAM Mode Table 11-5 describes ORx fields in SDRAM mode. For more details, see Section 11.4.12, “SDRAM Configuration Examples.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-15...
Page 434 010 11 row address lines 011 12 row address lines 100 13 row address lines 101 14 row address lines 110 15 row address lines 111 16 row address lines MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-16 Freescale Semiconductor...
Page 435: Orx —Gpcm Mode
AM can be read or written at any time. Note: After system reset, OR0[AM] is 1111_1110_0000_0000_0. 17–18 — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-17...
Page 436 00 Normal timing is generated by the memory controller. No additional cycles are inserted. 01 One idle clock cycle is inserted. 10 Four idle clock cycles are inserted. (default) 11 Eight idle clock cycles are inserted. — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-18 Freescale Semiconductor...
Page 437: Orx—Upm Mode
0 BCTL x and LWR are asserted upon an access to the current memory bank. 1 BCTL x and LWR are not asserted upon an access to the current memory bank. 20–22 — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-19...
Page 438: X Sdram Mode Register (Psdmr)
LDOTOPRE EAMUX BUFCMD Reset 0000_0000_0000_0000 Addr 0x10192 (PSDMR), 0x10196 (LSDMR) Figure 11-10. 60x/Local SDRAM Mode Register (PSDMR/LSDMR) Table 11-8 describes PSDMR fields. LSMDR fields are described in Table 11-9.. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-20 Freescale Semiconductor...
Page 439 000 A10 001 A11 001 A9 010 A10 010 A8 011 A9 011 A7 100 A8 100 A6 101 A7 101 A5 110 A6 110 A4 111 A5 111 A3 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-21...
Page 440 SDRAM. See Section 11.4.6.5, “Last Data In to Precharge—Write Recovery.” 01 1 clock cycles 10 2 clock cycles 11 3 clock cycles 00 4 clock cycles MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-22 Freescale Semiconductor...
Page 441: Local Bus Sdram Mode Register (Lsdmr)
0 Bank-based interleaving 1 Page-based interleaving (normal operation) RFEN Refresh enable. Indicates that the SDRAM requires refresh services. 0 Refresh services are not required 1 Refresh services are required MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-23...
Page 442 000 A10 001 A11 001 A9 010 A10 010 A8 011 A9 011 A7 100 A8 100 A6 101 A7 101 A5 110 A6 110 A4 111 A5 111 A3 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-24 Freescale Semiconductor...
Page 443 SDRAM. See Section 11.4.6.5, “Last Data In to Precharge—Write Recovery.” 01 1 clock cycles 10 2 clock cycles 11 3 clock cycles 00 4 clock cycles MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-25...
Page 444: Machine A/B/C Mode Registers (Mxmr)
Field RLFx WLF x TLF x Reset 0000_0000_0000_0000 Addr 0x10172 (MAMR); 0x10176 (MBMR); 0x1017A (MCMR) Figure 11-11. Machine x Mode Registers (M x MR) Table 11-10 describes MxMR bits. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-26 Freescale Semiconductor...
Page 445 Note: To avoid conflicts between successive accesses to different memory regions, the minimum pattern in the RAM array for a request serviced should not be shorter than the period established by DS x . MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-27...
Page 446: Memory Data Register (Mdr)
11-12, contains data written to or read from the RAM array for UPM commands. MDR must be set up before issuing a write command to the READ WRITE UPM. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-28 Freescale Semiconductor...
Page 447: Memory Address Register (Mar)
The memory address register (MAR) is shown in Figure 11-13. Field Reset xxxx_xxxx_xxxx_xxxx Addr 0x0x10168 Field Reset xxxx_xxxx_xxxx_xxxx Addr 0x10116A Undefined at reset. Figure 11-13. Memory Address Register (MAR) Table 11-12 describes MAR fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-29...
Page 448: X Bus-Assigned Upm Refresh Timer (Purt)
The local bus assigned UPM refresh timer register (LURT) is shown in Figure 11-15. Field LURT Reset 0000_0000 Addr 0x0x101A0 Figure 11-15. Local Bus-Assigned UPM Refresh Timer (LURT) Table 11-14 describes LURT fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-30 Freescale Semiconductor...
Page 449: X Bus-Assigned Sdram Refresh Timer (Psrt)
MPTPR[PTP] = 31, the PSRT value should be 11decimal. (12*32)/25 MHz = 15.36 µs, which is less than the required service period of 15.6 µs. 11.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT) The local bus-assigned SDRAM refresh timer register (LSRT) is shown in Figure 11-17. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-31...
Page 450: Memory Refresh Timer Prescaler Register (Mptpr)
Refresh timers prescaler. Determines the period of the memory refresh timers input clock. It divides the bus clock. Prescaler clock frequency = Bus frequency / (PTP + 1). 8–15 — Reserved, should be cleared MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-32 Freescale Semiconductor...
Page 451: X Bus Error Status And Control Registers (Tescrx)
Figure 11-19. shows an eight-bank, 128-Mbyte system. Each bank consists of eight 2 x 1-Mbit x 8 SDRAMs. Note that the SDRAM memory clock must operate at the same frequency as, and be phase-aligned with, the system clock. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-33...
Page 452: Mbyte Sdram (Eight-Bank Configuration, Banks 1 And 8 Shown)
ADDR[0–11] ADDR[0–11] DQ[0–7] DQ[0–7] DATA[0–7] DATA[56–63] 2x1M x8 2x1M x8 SDRAM SDRAM ADDR[0–11] ADDR[0–11] DQ[0–7] DQ[0–7] DATA[0–7] DATA[56–63] Figure 11-19. 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-34 Freescale Semiconductor...
Page 453: Supported Sdram Configurations
PowerQUICC II bus clock. Data at the output of the SDRAM device must be sampled on the rising edge of the PowerQUICC II bus clock. As seen in Table 11-19, the PowerQUICC II provides the following SDRAM interface commands: MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-35...
Page 454: Page-Mode Support And Pipeline Accesses
If ETM/LETM = 1, the use of SDRAM pipelining also allows for back-to-back data phases to occur with zero clocks of separation for CPM accesses and with one clock of separation for core accesses, as required by the 60x bus specification. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-36 Freescale Semiconductor...
Page 455: Bank Interleaving
PL/SDMR[SDAM] and PL/SDMR[BSMA]. Table 11-20. shows how P/LSDMR[SDAM] settings affect address multiplexing. For the effect of PL/SDMR[BSMA] see Section 11.4.12, “SDRAM Configuration Examples.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-37...
Page 456: Sdram Device-Specific Parameters
Activate to read/write interval (P/LSDMR[ACTTORW]). See Section 11.4.6.2, “Activate to Read/Write Interval.” • CAS latency, column address to first data out (P/LSDMR[CL]). See Section 11.4.6.3, “Column Address to First Data Out—CAS Latency.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-38 Freescale Semiconductor...
Page 457: Precharge-To-Activate Interval
Figure 11-20. PRETOACT = 2 (2 Clock Cycles) 11.4.6.2 Activate to Read/Write Interval As represented in Figure 11-21, this parameter, controlled by P/LSDMR[ACTTORW], defines the earliest timing for command after an command. READ WRITE ACTIVATE MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-39...
Page 458: Column Address To First Data Out—Cas Latency
SDRAM. Activate Read First data out CL = 2 SDRAS SDCAS Column MA[0–11] DQMn Data Figure 11-22. CL = 2 (2 Clock Cycles) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-40 Freescale Semiconductor...
Page 459: Last Data Out To Precharge
SDRAM. PRECHARGE Activate WRITE Last data in Deactivate WRC = 2 SDRAS SDCAS Column MA[0–11] Data Figure 11-24. WRC = 2 (2 Clock Cycles) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-41...
Page 460: Refresh Recovery Interval (Rfrc)
In 60x-compatible mode, external buffers may be placed on the command strobes, except CS, as well as the address lines. If the additional delay of the buffers is endangering the device setup time, MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-42...
Page 461: Sdram Interface Timing
SDRAM Interface Timing Figure 11-28 through Figure 11-36 show SDRAM timing for various types of accesses. SDRAS SDCAS Column MA[0–11] Data Figure 11-28. SDRAM Single-Beat Read, Page Closed, CL = 3 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-43...
Page 462: Sdram Single-Beat Read, Page Hit, Cl = 3
* BS—Bank select according to SDRAM organization. A10 = 1 means all banks are precharged. CAS Latency = 3 Figure 11-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-44 Freescale Semiconductor...
Page 463: Sdram Single-Beat Write, Page Hit
Figure 11-33. SDRAM Three-Beat Burst Write, Page Closed SDRAS SDCAS Column1 Column2 MA[0–11] Data DQM latency (affects negation only) = 2 Figure 11-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-45...
Page 464: Sdram Read/Write Transactions
PowerQUICC II protects non-targeted addresses by driving DQMn high on the irrelevant cycles of the burst. However, system performance is not compromised since, if a new transaction is pending, the PowerQUICC II begins executing it immediately, effectively terminating the burst early. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-46 Freescale Semiconductor...
Page 465: Sdram Refresh
The period of the refresh interval must be greater than the access time to ensure that read and write operations complete successfully. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-47...
Page 466: Sdram Refresh Timing
Activate RFRC SDRAS SDCAS MA[0–11] Data Figure 11-39. SDRAM Bank-Staggered CBR Refresh Timing 11.4.12 SDRAM Configuration Examples The following sections provide SDRAM configuration examples for page- and bank-based interleaving. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-48 Freescale Semiconductor...
Page 467: Sdram Configuration Example (Page-Based Interleaving)
READ WRITE Table 11-24. SDRAM Device Address Port during Command READ WRITE “A[0–14]” A[15–16] A[17] A[18] A[19] A[20–28] A[29–31] — Internal bank select Don’t care Don’t care Column n.c. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-49...
Page 468: Sdram Configuration Example (Bank-Based Interleaving)
The following parameters can be extracted: • PSDMR[PBI] = 0 • ORx[BPD] = 01—4 internal banks • ORx[ROWST] = 0100—row starts at A[8] • ORx[NUMR] = 011—there are 12 row lines MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-50 Freescale Semiconductor...
Page 469: General-Purpose Chip-Select Machine (Gpcm)
PRETOACT from device data sheet 11.5 General-Purpose Chip-Select Machine (GPCM) Users familiar with the MPC8xx memory controller should read Section 11.5.4, “Differences between MPC8xx’s GPCM and MPC82xx’s GPCM,” first. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-51...
Page 470: Gpcm-To-Sram Configuration
32-bit port size SRAM device and the PowerQUICC II. 32-Bit Wide SRAM PowerQUI 128K WE[0–3] WE[0–3] GPL_x1/OE A[15–29] Address D[0–31] Data Figure 11-40. GPCM-to-SRAM Configuration MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-52 Freescale Semiconductor...
Page 471: Timing Configuration
The banks selected to work with the GPCM support an option to output the CS line at different timings with respect to the external address bus. CS can be output in any of three configurations: • Simultaneous with the external address MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-53...
Page 472: Chip-Select And Write Enable Deassertion Timing
CS is connected directly to CE of the memory device. The WE signals are connected to the respective W signal in the memory device where each WE corresponds to a different data byte. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-54...
Page 473: Gpcm Memory Device Interface
Figure 11-44. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0) When ACS ≠ 00 and CSNT = 1, WE and CS are negated one quarter of a clock earlier, as shown in Figure 11-45. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-55...
Page 474: Relaxed Timing
Address PSDVAL ACS = 10 ACS = 11 BCTL x Data Figure 11-46. GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-56 Freescale Semiconductor...
Page 475: Gpcm Relaxed-Timing Write (Acs = 10, Scy = 0, Csnt = 1, Trlx = 1)
Clock Address CSNT = 1 PSDVAL ACS = 10 BCTL x Data Figure 11-48. GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-57...
Page 476: Output Enable (Oe) Timing
When TRLX = 1, the number of wait states inserted by the memory controller is defined by 2 x SCY or a maximum of 30 wait states. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-58 Freescale Semiconductor...
Page 477: Extended Hold Time On Read Accesses
Number of Hold Time Clock Cycles Figure 11-50 through Figure 11-53 for timing examples. Clock Address PSDVAL BCTL x Data Figure 11-50. GPCM Read Followed by Read (OR x [29–30] = 00, Fastest Timing) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-59...
Page 478: Gpcm Read Followed By Read (Orx[29–30] = 01)
Figure 11-51. GPCM Read Followed by Read (OR x [29–30] = 01) Clock Address PSDVAL BCTL x Data Hold Time Long hold time allowed Figure 11-52. GPCM Read Followed by Write (OR x [29–30] = 01) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-60 Freescale Semiconductor...
Page 479: External Access Termination
The user selects whether PSDVAL is generated internally or externally (by means of GTA assertion) by resetting/setting ORx[SETA]. Figure 11-54 shows how a GPCM access is terminated by GTA assertion. Asserting GTA terminates an access even if ORx[SETA] = 0 (internal PSDVAL generation). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-61...
Page 480: Boot Chip-Select Operation
Word.” PS From hard reset configuration word. See Section 5.4.1, “Hard Reset Configuration Word” DECC0 MS000 EMEMC From hard reset configuration word. See Section 5.4.1, “Hard Reset Configuration Word” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-62 Freescale Semiconductor...
Page 481: Differences Between Mpc8Xx's Gpcm And Mpc82Xx's Gpcm
The three user-programmable machines (UPMs) are flexible interfaces that connect to a wide range of memory devices. At the heart of each UPM is an internal-memory RAM array that specifies the logical MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 482: Requests
However, local bus accesses that hit a bank allocated to the 60x bus are ignored. 11.6.1 Requests An internal or external device’s request for a memory access initiates one of the following patterns (MxMR[OP] = 00): • Read single-beat pattern (RSS) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-64 Freescale Semiconductor...
Page 483: Ram Array Indexing
UPM Routine Routine Start Address Read single-beat (RSS) 0x00 Read burst (RBS) 0x08 Write single-beat (WSS) 0x18 Write burst (WBS) 0x20 Refresh timer (PTS) 0x30 Exception condition (EXS) 0x3C MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-65...
Page 484: Memory Access Requests
UPMC can be assigned to any bus; there is no need to program its refresh routine because it will use the one in UPMA or UPMB, according to the bus to which it is assigned. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-66...
Page 485: Exception Requests
If specified in the RAM, the value of the external signals can be changed after any of the positive edges of T[1–4], plus a circuit delay time as specified in the Hardware Specifications. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-67...
Page 486: Memory Controller Upm Clock Scheme For Integer Clock Ratios
TSIZn. The GPL lines toggle as programmed for any access that initiates a particular pattern, but resolution of control is limited to T1 and T3. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-68...
Page 487: The Ram Array
Figure 11-61. are UPM outputs. The selected CS is for the bank that matches the current address. The selected BS is for the byte lanes read or written by the access. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 488: Ram Words
UTA TODT LAST DLT3 WAEN Reset — Addr (All 32 bits of the RAM word are addressed as shown in the address row above.) Figure 11-62. The RAM Word MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-70 Freescale Semiconductor...
Page 489 10 The value of the GPL0 line at the rising edge of T3 will be 0 11 The value of the GPL0 line at the rising edge of T3 will be 1 Section 11.6.4.1.3, “General-Purpose Signals (GxTx, GOx).” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-71...
Page 490 0 The UPMWAITx function is disabled. 1 A freeze in the external signal’s logical value occurs if the external wait signal is detected asserted. This condition lasts until UPMWAITx is negated. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-72 Freescale Semiconductor...
Page 491 10 A[0–31] is the address requested by the internal master multiplexed according to M x MR[AM x ]. For example, row address. 11 A[0–31] is the contents of MAR. Used for example, during SDRAM mode initialization. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-73...
Page 492: Chip-Select Signals (Cxtx)
CS signal. The state of the selected CSx signal of the corresponding bank depends on the value of each CSTn bit. Figure 11-63 and the timing diagrams in Figure 11-60 show how UPMs control CS signals. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-74 Freescale Semiconductor...
Page 493: Byte-Select Signals (Bxtx)
D[8–15] contains valid data, BS2 indicates that D[16–23] contains valid data, and BS3 indicates that D[24–31] contains valid data during a cycle, and so forth. Note that for a refresh timer request, all the BS signals are asserted/negated by the UPM. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-75...
Page 494: General-Purpose Signals (Gxtx, Gox)
REDO function. • LAST and REDO should not be set together. • REDO should not be used within the exception routine. Figure 11-79 shows an example of REDO use. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-76 Freescale Semiconductor...
Page 495: Address Multiplexing
If G4T4/DLT3 functions as G4T4, data is latched on the rising edge of CLKIN, as is normal in PowerQUICC II bus operation. Figure 11-65 shows data sampling that is controlled by the UPM. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-77...
Page 496: Signals Negation
CSx and GPL1 states (C12 and F) and the WAEN value (C) are frozen until UPMWAIT is recognized as deasserted. WAEN is typically set before the line that contain UTA = 1. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-78...
Page 497: Upm Dram Configuration Example
UPM DRAM Configuration Example Consider the following DRAM organization: • Eight 64Mbit devices, each organized as 8M x 8bits • Each device has 12 row lines and 9 column lines. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-79...
Page 498: Differences Between Mpc8Xx Upm And Mpc82Xx Upm
UPM signals at end of an access, those signals kept their previous value. In the PowerQUICC II, all UPM signals are negated (CS,BS,GPL[0:4] driven to logic 1 and GPL5 driven MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-80...
Page 499: Memory System Interface Example Using Upm
A[19–28] A[0–9] D[0–15] D[0–15 D[0–63] D[0–15] D[0–15] CAS[0–1] CAS[0–1] A[0–9] A[0–9] 1M x 16 1M x 16 Figure 11-67. DRAM Interface Connection to the 60x Bus (64-Bit Port Size) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-81...
Page 500 UPM can than be written through use of the MxMR[OP] = 11. Figure 11-56 shows the first locations addressed by the UPM, according to the different services required by the DRAM. CLKIN Column 1 RD/WR PSDVAL (RAS) (CAS) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-82 Freescale Semiconductor...
Page 501: Single-Beat Read Access To Fpm Dram
Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 Figure 11-68. Single-Beat Read Access to FPM DRAM CLKIN Column 1 RD/WR PSDVAL (RAS) (CAS) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-83...
Page 502: Single-Beat Write Access To Fpm Dram
Bit 30 last Bit 31 WSS+1 WSS+2 Figure 11-69. Single-Beat Write Access to FPM DRAM CLKIN Column 1 Column 2 Column 3 Column 4 RD/WR PSDVAL (RAS) (CAS) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-84 Freescale Semiconductor...
Page 503: Burst Read Access To Fpm Dram (No Loop)
RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 Figure 11-70. Burst Read Access to FPM DRAM (No LOOP) CLKIN Column 1 Column 2 Column 3 Column 4 RD/WR PSDVAL (RAS) (CAS) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-85...
Page 504: Burst Read Access To Fpm Dram (Loop)
Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 Figure 11-71. Burst Read Access to FPM DRAM (LOOP) CLKIN Column 1 Column 2 Column 3 Column 4 RD/WR PSDVAL (RAS) (CAS) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-86 Freescale Semiconductor...
Page 505: Burst Write Access To Fpm Dram (No Loop)
Bit 30 last Bit 31 WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 Figure 11-72. Burst Write Access to FPM DRAM (No LOOP) CLKIN RD/WR PSDVAL (RAS) (CAS) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-87...
Page 506: Refresh Cycle (Cbr) To Fpm Dram
Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 Figure 11-73. Refresh Cycle (CBR) to FPM DRAM CLKIN RD/WR PSDVAL (RAS) (CAS) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-88 Freescale Semiconductor...
Page 507: Exception Cycle
Disable timer period M x MR[DS x ] 0b01 Select between GPL4 and UPMWAIT = UPMWAIT, data sampled at clock M x MR[GPL_x4DIS] negative edge Burst inhibit device OR x [BI] MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-89...
Page 508 Memory Controller The timing diagram in Figure 11-75 shows how the burst-read access shown in Figure 11-70 can be reduced. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-90 Freescale Semiconductor...
Page 509: Fpm Dram Burst Read Access (Data Sampling On Falling Edge Of Clkin)
Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 Figure 11-75. FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-91...
Page 510: Edo Interface Example
BR x [WP] Refresh timer prescaler MPTPR 0x04 Refresh timer value (1024 refresh cycles) PURT[PURT] 0x07 Refresh timer enable M x MR[RFEN] Address multiplex size M x MR[AM x ] 0b001 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-92 Freescale Semiconductor...
Page 511 Memory Controller Table 11-44. EDO Connection Field Value Example (continued) Explanation Field Value Disable timer period M x MR[DS x ] 0b10 Burst inhibit device OR x [BI] MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-93...
Page 512: Single-Beat Read Access To Edo Dram
Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 RSS+3 RSS+4 Figure 11-77. Single-Beat Read Access to EDO DRAM MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-94 Freescale Semiconductor...
Page 513: Single-Beat Write Access To Edo Dram
Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS+1 WSS+2 WSS+3 Figure 11-78. Single-Beat Write Access to EDO DRAM MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-95...
Page 514: Single-Beat Write Access To Edo Dram Using Redo To Insert Three Wait States
Bit 29 todt Bit 30 last Bit 31 WSS+1 WSS+2 REDO1 REDO2 REDO3 WSS+3 Figure 11-79. Single-Beat Write Access to EDO DRAM Using REDO to Insert Three Wait States MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-96 Freescale Semiconductor...
Page 515: Burst Read Access To Edo Dram
Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 RBS+9 RBS+10 Figure 11-80. Burst Read Access to EDO DRAM MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-97...
Page 516: Burst Write Access To Edo Dram
Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 WBS+9 Figure 11-81. Burst Write Access to EDO DRAM MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-98 Freescale Semiconductor...
Page 517: Refresh Cycle (Cbr) To Edo Dram
Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 PTS+3 PTS+4 Figure 11-82. Refresh Cycle (CBR) to EDO DRAM MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-99...
Page 518: Exception Cycle For Edo Dram
Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 Figure 11-83. Exception Cycle For EDO DRAM MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-100 Freescale Semiconductor...
Page 519: Handling Devices With Slow Or Variable Access Times
External bus master support is available only if the PowerQUICC II is placed in 60x-compatible mode by setting BCR[EBM]; see Section 4.3.2.1, “Bus Configuration Register (BCR).” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-101...
Page 520: X-Compatible External Masters (Non-Powerquicc Ii)
These signals are latched by the memory controller and on subsequent clock cycles, BADDR[27–31] increments as programmed in the UPM or after each data beat MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-102...
Page 521: External Masters Timing
The memory controller asserts ALE only on the start of new memory controller access. Figure 11-84 shows the pipelined bus operation in 60x-compatible mode. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-103...
Page 522: Pipelined Bus Operation And Memory Access In 60X-Compatible Mode
1-cycle delay for external master access. For systems that use the 60x bus with low frequency (33 MHz), the 1-cycle delay for external masters can be eliminated by setting BCR[EXDD]. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-104...
Page 523: Example Of External Master Using The Sdram Machine
PowerQUICC II can share access to a SDRAM bank. Note that the address multiplexer is controlled by SDAMUX, while the address latch is controlled by ALE. Also note that because this is a 64-bit port size SDRAM, BADDR is not needed. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 11-105...
Page 524: External Master Configuration With Sdram Device
SDAMUX Multiplexer Latch PowerQUICC II External Master A[0–31] D[0–63] TT[0–4] TBST TSIZ[1–3] TSIZ[0–2] (pull down) TSIZ[0] PSDVAL (pull up) Arbitration signals Figure 11-86. External Master Configuration with SDRAM Device MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 11-106 Freescale Semiconductor...
Page 525: L2 Cache Configurations
PowerQUICC II can also support additional bus masters (60x or PowerQUICC II type) in copy-back mode. Figure 12-1. shows a PowerQUICC II connected to a MPC2605 integrated L2 cache in copy-back mode. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 12-1...
Page 526: Write-Through Mode
L2 cache are serviced from the L2 cache without requiring a memory transaction and its associated latency. Thus, reads are serviced just as they are for copy-back mode. Write-through MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 12-2...
Page 527 (60x or PowerQUICC II type) in write-through mode. Figure 12-2. shows a PowerQUICC II connected to a MPC2605 integrated L2 cache in write-through mode. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 12-3...
Page 528: Ecc/Parity Mode
The PowerQUICC II’s DP[0:7] signals are connected to the L2 cache’s DP[0:7] signals. • The L2’s TSIZ[0:2] signals are pulled down to always indicate 8-byte transaction size. • The L2’s A[29:31] signals are pulled down. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 12-4 Freescale Semiconductor...
Page 529 Section 11.9, “External Master Support (60x-Compatible Mode),” for more information about external master types. Figure 12-3. shows a PowerQUICC II connected to an MPC2605 integrated L2 cache in ECC/Parity mode. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 12-5...
Page 530: L2 Cache Interface Parameters
PowerQUICC II’s L2 interface. The parameters should be configured as follows: • BCR[EBM] = 1—PowerQUICC II in 60x-compatible mode. • BCR[L2C] = 1—L2 cache is present. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 12-6 Freescale Semiconductor...
Page 531: System Requirements When Using The L2 Cache Interface
TS. The PowerQUICC II samples L2_HIT when L2D expires. In the second transaction (A1), the access misses in the L2 cache and the memory controller starts the transaction a minimum of three cycles after the assertion of TS. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 12-7...
Page 532: Read Access With L2 Cache
Secondary (L2) Cache Support Addr A0 & TBST& CI A1 & TBST disabled active Memc controls AACK PowerQUICC II DATA L2D = 0 L2 HIT Figure 12-4. Read Access with L2 Cache MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 12-8 Freescale Semiconductor...
Page 533: Overview
The PowerQUICC II’s implementation includes a TAP controller, a 4-bit instruction register, and two test registers (a 1-bit bypass register and a 475-bit boundary scan register). Figure 13-1 shows an overview of the PowerQUICC II’s scan chain implementation. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 13-1...
Page 534: Tap Controller
JTAG logic. The value shown adjacent to each bubble represents the value of the TMS signal sampled on the rising edge of the TCK signal. Figure 13-2 shows the state machine. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 13-2 Freescale Semiconductor...
Page 535: Boundary Scan Register
(a logic value or high impedance) of the bidirectional and three-state signal pins. Figure 13-3, Figure 13-4, Figure 13-5, and Figure 13-6 show various cell types. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 13-3...
Page 536: Output Pin Cell (O.pin)
Update DR Figure 13-3. Output Pin Cell (O.Pin) To Next Cell Data to Input System Logic Shift DR Clock DR From Last Cell Figure 13-4. Observe-Only Input Pin Cell (I.Obs) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 13-4 Freescale Semiconductor...
Page 537: Instruction Register
(HI-Z) can be used to disable all device output drivers. The PowerQUICC II includes an 8-bit instruction register (no parity) that consists of a shift register with four parallel outputs. Data is transferred MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 538 TCK in the capture-DR controller state. Thus, the first bit to be shifted out after selecting the bypass register is always a logic zero. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 13-6 Freescale Semiconductor...
Page 539: Powerquicc Ii Restrictions
This is done inside the chip by connecting TRST to PORESET TMS should remain logic high, so that the TAP controller does not leave the test-logic-reset state. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 540 IEEE 1149.1 Test Access Port MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 13-8 Freescale Semiconductor...
Page 541: Communications Processor Module
PowerQUICC II implementation of universal asynchronous receiver transmitter (UART) protocol that is used for sending low-speed data between devices. • Chapter 22, “SCC HDLC Mode,” describes the PowerQUICC II implementation of HDLC protocol. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor IV-1...
Page 542 PowerQUICC II implementation of the inter-integrated circuit (I C®) controller, which allows data to be exchanged with other I C devices, such as microcontrollers, EEPROMs, real-time clock devices, and A/D converters. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 IV-2 Freescale Semiconductor...
Page 543 Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For example, MSR[LE] refers to the little-endian mode enable bit in the machine state register. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor IV-3...
Page 544 Table i contains acronyms and abbreviations used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 IV-4 Freescale Semiconductor...
Page 545 Register used for determining the source of a DSI exception Effective address EEST Enhanced Ethernet serial transceiver EPROM Erasable programmable read-only memory Free buffer pool FIFO First-in-first-out (buffer) General circuit interface MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor IV-5...
Page 546 Machine state register Not a number Network interface card Network interface unit NMSI Nonmultiplexed serial interface Non-real time Open systems interconnection Peripheral component interconnect Protocol data unit Peak cell rate MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 IV-6 Freescale Semiconductor...
Page 547 Translation lookaside buffer Time-slot assigner Transmit Unspecified bit rate UBR+ Unspecified bit rate with minimum cell rate guarantee UART Universal asynchronous receiver/transmitter User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter Wide area network MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor IV-7...
Page 548 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 IV-8 Freescale Semiconductor...
Page 549: Features
Four full-duplex serial communications controllers (SCCs) support the following protocols: — IEEE 802.3/Ethernet — High level/synchronous data link control (HDLC/SDLC) — LocalTalk (HDLC-based local area network protocol) — Universal asynchronous receiver transmitter (UART) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 14-1...
Page 550 Eight TC layers between the TDMs and FCC2 (MPC8264 and MPC8266 only) • Eight independent baud rate generators (BRGs) • Four general-purpose 16-bit timers or two 32-bit timers • General-purpose parallel ports—sixteen parallel I/O lines with interrupt capability MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-2 Freescale Semiconductor...
Page 551: Powerquicc Ii Serial Configurations
PowerQUICC II Serial Configurations The PowerQUICC II offers a flexible set of communications capabilities. A subset of the possible configurations using an PowerQUICC II is shown in Table 14-1. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 14-3...
Page 552: Communications Processor (Cp)
The following is a list of the CP’s important features. • One system clock cycle per instruction • 32-bit instruction object code • Executes code from internal ROM or RAM • 32-bit ALU data path MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-4 Freescale Semiconductor...
Page 553: Cp Block Diagram
The CP also gives SDMA commands to the SDMA. The CP interfaces with the dual-port RAM for loading and storing data and for fetching instructions while running microcode from dual-port RAM. Figure 14-2 shows the CP block diagram. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 14-5...
Page 554: G2 Core Interface
Dual-Port RAM Address Data Interface 60x Bus Local Bus Figure 14-2. Communications Processor (CP) Block Diagram 14.3.4 G2 Core Interface The CP communicates with the G2 core in several ways: MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-6 Freescale Semiconductor...
Page 555: Peripheral Interface
IDMA[1–4] emulation (default—option 1) Emergency (from FCCs, MCCs, and SCCs) IDMA[1–4] emulation (option 2) FCC1 receive FCC1 transmit MCC1 receive MCC2 receive MCC1 transmit MCC2 transmit FCC2 receive FCC2 transmit FCC3 receive MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 14-7...
Page 556: Execution From Ram
RISC Controller Configuration Register (RCCR) The RISC controller configuration register (RCCR), as shown in Figure 14-3, configures the CP to run microcode from ROM or RAM and controls the CP’s internal timer. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-8 Freescale Semiconductor...
Page 557: Risc Controller Configuration Register (Rccr
00 DREQ x has more priority than the communications controllers (default). 30–31 01 DREQ x has less priority than the communications controllers (option 2). 10 DREQ x has the lowest priority (option 3). 11 Reserved MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 14-9...
Page 558 1001 Microcode uses 8 Kbytes starting from dual-port RAM address 0x4000. Note: All other configurations not listed are reserved. 20, 21, EDM x Edge detect mode. DREQ x asserts as follows: 22, 23 0 Low-to-high change 1 High-to-low change MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-10 Freescale Semiconductor...
Page 559: Risc Time-Stamp Control Register (Rtscr)
RTPS Time-stamp timer pre-scale. Must be programmed to generate a 1-µs period input clock to the time-stamp timer. (Time-stamp frequency = (CPM frequency)/(RTPS+2) 14.3.9 RISC Time-Stamp Register (RTSR) The RISC time-stamp register (RTSR), shown in Figure 14-5, contains the time stamp. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 14-11...
Page 560: Risc Microcode Revision Number
For example, to terminate the transmission of an SCC’s frame without waiting until the end, a command must be issued through the CP command register (CPCR). STOP TX MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-12 Freescale Semiconductor...
Page 561: Cp Command Register (Cpcr)
(SI x ) or parallel I/O registers. 1–5 PAGE Indicates the parameter RAM page number associated with the sub-block being served. See the SBC description for page numbers. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 14-13...
Page 562: Cp Commands
MPC8250. Not available on the MPC8250 and the MPC8255. Not available on the MPC8250. 14.4.1.1 CP Commands The CP command opcodes are shown in Table 14-7. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-14 Freescale Semiconductor...
Page 563 IDMA 1100 — — — — — — — — — RANDOM NUMBER Undefined. Reserved for use by Freescale-supplied RAM microcodes. Not available on .29µm (HiP3) Rev A.1 devices. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 14-15...
Page 564 Section 19.9, “IDMA Commands.” START IDMA Section 19.9, “IDMA Commands.” STOP IDMA Set timer. Activates, deactivates, or reconfigures one of the 16 timers in the RISC timer table. SET TIMER MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-16 Freescale Semiconductor...
Page 565: Command Register Example
The worst-case command execution latency is 200 clocks and the typical command execution latency is about 40 clocks. 14.5 Dual-Port RAM The CPM static RAM (24 Kbyte on 0.29µm (HiP3) devices and 32 Kbyte on 0.25µm (HiP4) devices) is shown in Figure 14-7. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 14-17...
Page 566: Dual-Port Ram Block Diagram
BDs. However, when not used for microcode, the extra 8 Kbytes can be accessed from the 60x bus for general purpose internal storage. On .29µm (HiP3) revisions of the PowerQUICC II, this space is reserved. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-18 Freescale Semiconductor...
Page 567: Dual-Port Ram Memory Map
Only the parameters in the parameter RAM and the microcode RAM option require fixed addresses to be used. The BDs, buffer data, and scratchpad RAM can be located in the dual-port system RAM or in any MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 568: Buffer Descriptors (Bds)
The exact definition of the parameter RAM is contained in each protocol subsection describing a device that uses a parameter RAM. For example, the Ethernet parameter RAM is defined differently in some locations from the HDLC-specific parameter RAM. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-20 Freescale Semiconductor...
Page 569 Reserved 0x8AF8 RAND 0x8AFC C_BASE 0x8AFE IDMA4_BASE 12-16 0x8B00 Reserved 1280 Offset from RAM_BASE Reserved on the MPC8255. Reserved on the MPC8250 and the MPC8255. Refer to Table 14-5. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 14-21...
Page 570: Risc Timer Tables
Two areas of dual-port RAM, shown in Figure 14-9, are used for the RISC timer tables: • The RISC timer table parameter RAM • The RISC timer table entries MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-22 Freescale Semiconductor...
Page 571: Risc Timer Table Ram Usage
15 has not been serviced, then TM_CNT would not be updated in that tick interval. Offset from timer base address (0x8AE0) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 14-23...
Page 572: Risc Timer Command Register (Tm_Cmd)
An interrupt is generated only if the RISC timer table bit is set in the SIU interrupt mask register; see Section 4.3.1.5, “SIU Interrupt Mask Registers (SIMR_H and SIMR_L).” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-24 Freescale Semiconductor...
Page 573: Risc Timer Initialization Sequence
If the timer is being disabled, the parameters (other than the timer number) are ignored. 8. Issue the command by writing 0x29E1_0008 to the CPCR. SET TIMER 9. Repeat the preceding two steps for each timer to be enabled or disabled. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 14-25...
Page 574: Risc Timer Initialization Example
Otherwise, it clears R_TMV. Once the timer table scanning has completed, the CP updates the TM_CNT value in the RISC timer table parameter RAM and stops working on the timer tables until the next tick. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-26 Freescale Semiconductor...
Page 575: Using The Risc Timers To Track Cp Loading
96% utilization level. NOTE General-purpose timers are up counters, but RISC timers are down counters. The user should take this under consideration when comparing timer counts. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 14-27...
Page 576 Communications Processor Module Overview MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 14-28 Freescale Semiconductor...
Page 577 (SI1 and SI2), can be programmed to handle eight TDM lines concurrently with the same flexibility described in this manual. TDM channels on SI1 are referred to as TDMa1, TDMb1, TDMc1, TDMd1; TDM channels on SI2 are TDMa2, TDMb2, TDMc2, TDMd2. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-1...
Page 578: Si Block Diagram
If the TSA is not used as intended, it can be used to generate complex wave forms on dedicated output pins. For instance, it can program these pins to implement stepper motor control or variable-duty cycle and period control on-the-fly. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-2 Freescale Semiconductor...
Page 579: Features
Arbitrary mapping of any TDM time slots • Can connect up to four independent TDM channels. Each TDM channel can support up to 128 channels (all four channels can support up to 128 channels together). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-3...
Page 580: Overview
Finally, the user can provide separate receive and transmit syncs as well as clocks. Figure 15-2 shows example TSA configurations ranging from the simplest to the most complex. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-4 Freescale Semiconductor...
Page 581: Various Configurations Of A Single Tdm Channel
PowerQUICC II 1 TDM Sync 1 TDM Clock SCC2 SMC1 SCC2 TDM Tx 1 TDM Sync 1 TDM Clock TDM Rx Figure 15-2. Various Configurations of a Single TDM Channel MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-5...
Page 582: Dual Tdm Channel Example
PowerQUICC II and are not associated with the dual-port RAM. One SIx RAM is always used to program the transmit routing; the other is always used MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-6...
Page 583: Enabling Connections To Tsa
TSA and the serial interfaces. The connection is made by programming the CPM mux. See Chapter 16, “CPM Multiplexing.” Once the connections are made, the exact routing decisions are made in the SIx RAM. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-7...
Page 584: Serial Interface Ram
RAM has a shadow for changing SIx RAM entries while the TDM channel is active. This reduces the number of available SIx RAM entries for that TDM. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-8 Freescale Semiconductor...
Page 585: One Multiplexed Channel With Static Frames
After programming the shadow RAM, the user sets SIxCMDR[CSRxn] for the associated channel. When the next frame sync arrives, the SI automatically exchanges the current-route RAM for the shadow RAM. Section 15.4.5, “Static and Dynamic Routing.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-9...
Page 586: Programming Six Ram Entries
BYT LST Addr Chapter 3, “Memory Map.” Figure 15-7. SI x RAM Entry Fields When MCC = 0, the SIx RAM entry fields function as described in Table 15-1. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-10 Freescale Semiconductor...
Page 587 11–13 Count. Indicates the number of bits/bytes (according to the BYT bit) that the routing and strobe select of this entry controls. 000 = 1 bit/byte; 111= 8 bits/bytes. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-11...
Page 588: Using The Swtr Feature
SWTR feature can cause erratic behavior. Also note, this feature does not work with nibble operation. When MCC = 1, the SIx RAM entry fields function as described in Table 15-2. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-12 Freescale Semiconductor...
Page 589 Also note that, to avoid errors in switching to and from shadow SI RAM, the last entry in SI RAM should not be programmed to 1-bit resolution (i.e. CNT = 000 and BYT = 0). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 590: Six Ram Programming Example
SIx RAM to use the same clock and sync to simultaneously control both sets of SIx RAM entries. 15.4.5 Static and Dynamic Routing The SIx RAM has two operating modes for the TDMs: MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-14 Freescale Semiconductor...
Page 591 The current-route and shadow SI RAMs of a given TDMx should be contiguous; that is, the current-route and shadow SI RAMs of differing TDMx should not be interleaved. An example is shown in Figure 15-9. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-15...
Page 592: Example: Six Ram Dynamic Changes, Tdma And B, Same Six Ram Size
64 RXa CSRRb=0 Shadow Route Shadow Route CSRTb=0 L1RCLKa L1RCLKb Framing Signals: L1RSYNCa L1RSYNCb Figure 15-9. Example: SI x RAM Dynamic Changes, TDMa and b, Same SI x RAM Size MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-16 Freescale Semiconductor...
Page 593: Serial Interface Registers
SIx RAM) to support any or all of the ISDN channels independently when in IDL or GCI mode. Any extra serial channel can then be used for other purposes. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-17...
Page 594: Si Mode Registers (Sixmr)
This mode is used to accomplish loopback testing of the entire TDM without affecting the external serial lines. Note: In modes 01, 10, and 11, the receive and transmit clocks should be identical. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-18 Freescale Semiconductor...
Page 595 See Figure 15-13, Figure 15-14, Figure 15-15, and Figure 15-16. 0 Falling edge. Use for IDL and GCI. 1 Rising edge. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-19...
Page 596: One-Clock Delay From Sync To Data (Xfsd = 01)
Figure 15-13. No Delay from Sync to Data ( x FSD = 00) Figure 15-14 shows the effects of changing FE when CE = 1 with a 1-bit frame sync delay. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-20 Freescale Semiconductor...
Page 597: Falling Edge (Fe) Effect When Ce = 1 And Xfsd = 01
Figure 15-15. Falling Edge (FE) Effect When CE = 0 and x FSD = 01 Figure 15-16 shows the effects of changing FE when CE = 1 with no frame sync delay. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-21...
Page 598: Falling Edge (Fe) Effect When Ce = 1 And Xfsd = 00
Figure 15-16. Falling Edge (FE) Effect When CE = 1 and x FSD = 00 Figure 15-17 shows the effects of changing FE when CE = 0 with no frame sync delay. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-22 Freescale Semiconductor...
Page 599: Six Ram Shadow Address Registers (Sixrsr)
The SIx RAM shadow address registers (SIxRSR), shown in Figure 15-18, define the starting addresses of the shadow section in the SIx RAM for each of the TDM channels. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-23...
Page 600: Si Command Register (Sixcmdr)
Field CSRRA CSRTA CSRRB CSRTB CSRRC CSRTC CSRRD CSRTD Reset 0000_0000 Addr 0x0x11B2A (SI1CMDR), 0x0x11B4A (SI2CMDR) Figure 15-19. SI Command Register (SI x CMDR) Table 15-7 describes SIxCMDR fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-24 Freescale Semiconductor...
Page 601: Si Status Registers (Sixstr)
IDL, data on three channels (B1, B2, and D) is transferred in a 20-bit frame, providing a full-duplex bandwidth of 160 Kbps. The PowerQUICC II is an IDL slave device that is clocked by the IDL bus master MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 602: Idl Interface Example
CODEC as a digital voice channel, if preferred. The SPI is used to send initialization commands and periodically check status from the S/T transceiver. The SMC connected to the terminal is configured for UART. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-26 Freescale Semiconductor...
Page 603: Idl Terminal Adaptor
IDL grant permission to transmit on the D Channel; input to the PowerQUICC II on the L1TSYNCx pin. Note: x = a, b, c, and d for TDMa, TDMb, TDMc, and TDMd (for SI1 and SI2). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-27...
Page 604: Idl Bus Signals
(L1RSYNCx) is asserted. If L1GRx is asserted, the PowerQUICC II sends the first zero of the opening flag in the first bit of the D channel. If a collision is detected on the D channel, the physical layer MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-28...
Page 605: Idl Interface Programming
Table 15-10. SI x RAM Entries for an IDL Interface SI x RAM Entry Entry Number SWTR SSEL CSEL Description 0000 0010 8-bit SCC2 0000 0001 1-bit SCC1 0000 0000 1-bit no support 0000 0101 4-bit SMC1 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-29...
Page 606: Serial Interface Gci Support
The PowerQUICC II fully supports the normal mode of the GCI, also known as the ISDN-oriented modular revision 2.2 (IOM-2), and the SCIT. The PowerQUICC II also supports the D-channel access control in S/T interface terminals using the command/indication (C/I) channel MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-30 Freescale Semiconductor...
Page 607: Gci Bus Signals
In addition to the 144-Kbps ISDN 2B+D channels, the GCI provides five channels for maintenance and control functions: • B1 is a 64-Kbps bearer channel • B2 is a 64-Kbps bearer channel MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-31...
Page 608: Si Gci Activation/Deactivation Procedure
The user can program more than one channel to interface to the GCI bus. Also, if the receive and transmit section are used for interfacing the same GCI bus, the user internally connects the receive clock and sync MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-32...
Page 609: Scit Programming
Skip 2 bits 0000 0111 D grant bit 2. SI1AMR = 0x00c0. TDMa is used in double speed clock and common Rx/Tx modes. SCIT mode is used in this example. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 15-33...
Page 610 18. SI1GMR = 0x11. Enable TDMa (one static TDM), STZ for TDMa. 19. SI1CMDR is not used. 20. SI1STR does not need to be read. 21. Enable the SCC1, SCC2, SMC1 and SMC2. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 15-34 Freescale Semiconductor...
Page 611 SI, the CMX connects that serial device to both SIs. Programming both SIs to use one serial device in the same time slot causes erratic behavior. Figure 16-1 shows a block diagram of the CMX. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 16-1...
Page 612: Cpm Multiplexing Logic (Cmx) Block Diagram
FCC2 can also be connected also to an 8-bit ATM UTOPIA level-2 interface (not on the MPC8250). • FCC2 can also be connected also to the TC layer (MPC8264 and MPC8266 only). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 16-2 Freescale Semiconductor...
Page 613: Enabling Connections To Tsa Or Nmsi
UTOPIA level-2 interface. Each SCC or SMC can be connected to the eight TDMs or to its own set of pins. Once connections are made to the TSA, the exact routing decisions are made in the SIx RAMs. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 614: Nmsi Configuration
Second, a group of serial receivers and transmitters that needs the same clock rate can share the same pin. This configuration leaves additional pins for other functions and minimizes potential skew between multiple clock sources. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 16-4 Freescale Semiconductor...
Page 615: Bank Of Clocks
The SMC transmitter and receiver share the same clock source when connected to the NMSI. Table 16-1 shows the clock source options for the serial controllers and TDM channels. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 16-5...
Page 616 TDMB1 TDMB1 Tx TDMC1 TDMC1 Tx TDMD1 TDMD1 Tx TDMA2 TDMA2 Tx TDMB2 TDMB2 Tx TDMC2 TDMC2 Tx TDMD2 TDMD2 Tx SMC1 Rx SMC1 Tx SMC2 Rx SMC2 Tx MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 16-6 Freescale Semiconductor...
Page 617: Cmx Registers
Master address output pin x connection. Note that the address indexes are relative to FCC1; see 6–7 Figure 16-7. 0 This address output pin is used by FCC2 in master mode. 1 This address output pin is used by FCC1 in master mode. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 16-7...
Page 618 For master mode: The user has two groups of eight address pins each. Three pins from each group are always connected to FCC1 and three are always connected to FCC2. The user decides which FCC uses the remaining two pins by programming CMXUAR[MADx]. See Figure 16-5. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 16-8 Freescale Semiconductor...
Page 619: Connection Of The Master Address
NOTE: To use FCC2 as shown, connect the FCC2 address bits reversed with respect to the pinout address indexes. PHY address pins with no pin connection should be connected to GND. Figure 16-6. Connection of the Slave Address MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 16-9...
Page 620 FCC1 and FCC2 receive multi-PHY addresses. The same diagram applies to the transmit multi-PHY bus using different dedicated parallel I/O pins. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 16-10 Freescale Semiconductor...
Page 621: Multi-Phy Receive Address Multiplexing
SAD2 SAD1 FCC2-RxAddr[2] (master) SAD0 FCC2-RxAddr[1] (master) FCC2 Rx Master Address FCC2-RxAddr[0] (master) ¬SAD0 ¬SAD1 FCC2 Rx Slave Address ¬SAD2 ¬SAD3 FCC2 ¬SAD4 Figure 16-7. Multi-PHY Receive Address Multiplexing MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 16-11...
Page 622: Cmx Si1 Clock Route Register (Cmxsi1Cr)
The CMX SI2 clock route register (CMXSI2CR), seen in Figure 16-9, defines the connection of SI2 to the clock sources that can be input from the bank of clocks. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 16-12 Freescale Semiconductor...
Page 623: Cmx Fcc Clock Route Register (Cmxfcr)
The CMX FCC clock route register (CMXFCR), shown in Figure 16-10, defines the connection of the FCCs to the TSA and to the clock sources from the bank of clocks. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 16-13...
Page 624: Cmx Fcc Clock Route Register (Cmxfcr)
011 FCC1 transmit clock is BRG8. 100 FCC1 transmit clock is CLK9. 101 FCC1 transmit clock is CLK10. 110 FCC1 transmit clock is CLK11. 111 FCC1 transmit clock is CLK12. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 16-14 Freescale Semiconductor...
Page 625 011 FCC3 receive clock is BRG8. 100 FCC3 receive clock is CLK13. 101 FCC3 receive clock is CLK14. 110 FCC3 receive clock is CLK15. 111 FCC3 receive clock is CLK16. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 16-15...
Page 626: Cmx Scc Clock Route Register (Cmxscr)
The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O control register. 1 SCC1 is connected to TSA of the SIs. The NMSIx pins are available for other purposes. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 16-16 Freescale Semiconductor...
Page 627 0 SCC3 transmitter does not support the grant mechanism. The grant is always asserted internally. 1 SCC3 transmitter supports the grant mechanism as determined by the GMx bit of a serial device channel. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 16-17...
Page 628 The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O control register. 1 SCC4 is connected to TSA of the SIs. The NMSIx pins are available for other purposes. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 16-18 Freescale Semiconductor...
Page 629: Cmx Smc Clock Route Register (Cmxsmr)
The choice of general-purpose I/O port pins versus SMCn pins is made in the parallel I/O control register. 1 SMC1 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes. — Reserved, should be cleared MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 16-19...
Page 630 00 SMC2 transmit and receive clocks are BRG2. 01 SMC2 transmit and receive clocks are BRG8. 10 SMC2 transmit and receive clocks are CLK19. 11 SMC2 transmit and receive clocks are CLK20. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 16-20 Freescale Semiconductor...
Page 631: Baud-Rate Generator (Brg) Block Diagram
C internal BRG. Alternatively, external clock pins can be configured as clock sources. The external source option allows flexible baud-rate frequency generation, independent of the system frequency. Additionally, the external source option allows a single external frequency to be the MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 17-1...
Page 632: Brg Configuration Registers 1–8 (Brgcx)
0x119F22 (BRGC1), 0x119F6 (BRGC2), 0x119FA (BRGC3), 0x119FE (BRGC4), 0x115F2 (BRGC5), 0x115F6 (BRGC6), 0x115FA (BRGC7), 0x115FE (BRGC8) Figure 17-2. Baud-Rate Generator Configuration Registers (BRGC x ) Table 17-1 describes the BRGCx fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 17-2 Freescale Semiconductor...
Page 633 DIV16 Divide-by-16. Selects a divide-by-1 or divide-by-16 prescaler before reaching the clock divider. See Section 17.3, “UART Baud Rate Examples.” 0 Divide by 1. 1 Divide by 16. Table 17-2 shows the possible external clock sources for the BRGs. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 17-3...
Page 634: Autobaud Operation On A Uart
BRG before the autobaud process begins. To do this, first clear BRGCx[ATB] and enable the BRG Rx clock to the highest frequency. Then, immediately before the autobaud process starts (after device initialization), set BRGCx[ATB]. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 17-4 Freescale Semiconductor...
Page 635: Uart Baud Rate Examples
For synchronous communication, the internal clock is identical to the baud-rate output. To get the preferred rate, select the system clock according to the following: BRGCLK or External Clock Source -------------------------------------------------------------------------------------------------- Sync Baud Rate • Prescale Divider Clock Divider + 1 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 17-5...
Page 636 ----------------------------------------------------------------------------------------------- - • BRGCx[DIV16] BRGCx[CD] + 1 For example, to get a rate of 64 kbps, the system clock can be 24.96 MHz, BRGCx[DIV16] = 0, and BRGCx[CD] = 389. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 17-6 Freescale Semiconductor...
Page 637: Timer Block Diagram
18.1 Features The key features of the timer include the following: • The maximum input clock is the bus clock • Maximum period of 4 seconds (at 66 MHz) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 18-1...
Page 638: General-Purpose Timer Units
TGATEx and disables the count on the rising edge of TGATEx. This mode allows the timer to count conditionally, based on the state of TGATEx. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 18-2...
Page 639: Cascaded Mode
These registers allow simultaneous starting and stopping of a pair of timers (1 and 2 or 3 and 4) if one bus cycle is used. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 640: Timer Global Configuration Register 1 (Tgcr1)
0 Reset the corresponding timer (a software reset is identical to an external reset). 1 Enable the corresponding timer if STP = 0. The TGCR2 register is shown in Figure 18-4. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 18-4 Freescale Semiconductor...
Page 641: Timer Mode Registers (Tmr1–Tmr4)
The four timer mode registers (TMR1–TMR4) are shown in Figure 18-5. Erratic behavior may occur if TGCR1 and TGCR2 are not initialized before the TMRs. Only TGCR[RST] can be modified at any time. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 18-5...
Page 642: Timer Reference Registers (Trr1–Trr4)
Each timer reference register (TRR1–TRR4), shown in Figure 18-6, contains the timeout’s reference value. The reference value is not reached until TCNx increments to equal the timeout reference value. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 18-6 Freescale Semiconductor...
Page 643: Timer Capture Registers (Tcr1–Tcr4)
TERx[REF] regardless of the corresponding TMRx[ORI]. The capture event is set only if it is enabled by TMRx[CE]. TER1–TER4 can be read at any time. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 18-7...
Page 644: Timer Event Registers (Ter1–Ter4)
Output reference event. The counter has reached the TRR value. TMR[ORI] is used to enable the interrupt request caused by this event. Capture event. The counter value has been latched into the TCR. TMR[CE] is used to enable generation of this event. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 18-8 Freescale Semiconductor...
Page 645: Sdma Data Paths
Thus, the local bus transfer occurs at the same time as other operations on the external 60x system bus. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 646: Sdma Bus Arbitration And Bus Transfers
An SDMA can steal transactions with no arbitration overhead when the PowerQUICC II is bus master. Figure 19-2 shows an SDMA stealing a transaction from an internal bus master. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-2 Freescale Semiconductor...
Page 647: Sdma Registers
This bit is cleared writing a 1; writing a zero has no effect. The SDMA transfer error address is read from PDTEA. The channel number is read from PDTEM. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 648: Sdma Mask Register (Sdmr)
See the SBC field description of the CPCR in Section 14.4.1, “CP Command Register (CPCR).” MSNUM[7] Bit 7 of MSNUM indicates which section of the peripheral controller is accessing the bus. 0 Transmit section 1 Receive section MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-4 Freescale Semiconductor...
Page 649: Idma Emulation
STOP IDMA • Any channel is independently configurable for data transfer from any 60x, local bus, or PCI source to any 60x, local bus, or PCI destination MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-5...
Page 650: Idma Transfers
Table 19-3. IDMA Transfer Parameters Parameter Description DMA_WRAP Determines the size of the dedicated IDMA transfer buffer in dual-port RAM. The buffer size is a multiple of a 60x burst size (k*32 bytes). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-6 Freescale Semiconductor...
Page 651: Idma Transfer Buffer In The Dual-Port Ram
1–31 bytes written in single accesses. The last transfers, read/write or both can be accompanied with DONE assertion, if programmed. Figure 19-6 shows an example of the three IDMA transfer stages. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-7...
Page 652: External Request Mode
DREQ triggers one read transfer automatically followed by one write transfer. NOTE External request mode does not support external DONE signaling from a device and DACK signaling from an IDMA channel. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-8 Freescale Semiconductor...
Page 653: Normal Mode
For single-address accesses (fly-by mode), the data is transferred directly between memory and the peripheral. Memory responds to the address phase, while the peripheral ignores it and responds to DACK assertions. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-9...
Page 654: Dual-Address Transfers
Section 19.8.2.1, “DMA Channel Mode (DCM).” In fly-by mode, an internal transfer buffer is not needed because the data is transferred directly between memory and the peripheral. Also, parameters MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-10 Freescale Semiconductor...
Page 655: Peripheral-To-Memory Fly-By Transfers
DMA bus latency, because the DMA controller does not release the 60x bus until the transfer is completed. If the DMA priority on the 60x bus is high, however, other 60x masters may experience a high bus latency. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 656: Pci Burst Length And Latency Control
The IDMA transfer size parameters give high flexibility to the user but it recommended to check the overall performance of the system with different IDMA parameters setting for maximum throughput. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-12 Freescale Semiconductor...
Page 657: Idma Priorities
Pull down (pull-up does not help) the DREQ inputs before programming the parallel port DREQ pins and until after setting the IDMA registers, or program the IDMA registers for a dummy transaction before programming the parallel port DREQ pins. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-13...
Page 658: Level-Sensitive Mode
CPM_CLK = 133MHz, with an approximate clock cycle of 7.5ns. Therefore, T = 15ns and DREQ must be negated no later than 15ns after the first rising edge of the bus clock after CS negation for the peripheral. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-14 Freescale Semiconductor...
Page 659: Edge-Sensitive Mode
DONE is ignored if it is asserted externally during internal request mode (DCM[ERM] = 0). DONE must not be asserted externally during memory-to-memory transfers if external request mode is enabled (DCM[ERM] = 1). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-15...
Page 660: Idma Operation
Auto Buffer and Buffer Chaining The core processor should initialize the IDMA BD table with the appropriate buffer handling mode, source address, destination address, and block length. See Figure 19-8. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-16 Freescale Semiconductor...
Page 661: Idmax Parameter Ram
(IDMAx_BASE) located in the parameter RAM; see Section 14.5.2, “Parameter RAM.” For example, if the IDMA1 channel parameter table is to be placed at address offset 0x2000 in the dual-port RAM, write 0x2000 to IDMA1_BASE. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-17...
Page 662 SEOB Hword Source end of burst. Used for alignment of the first read burst. 0x14 DEOB Hword Destination end of burst. Used for alignment of the first write burst. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-18 Freescale Semiconductor...
Page 663: Dma Channel Mode (Dcm)
RAM, that controls the operation modes of the IDMA channel. As are all other IDMA parameters, the DCM is undefined at reset. Field — — DMA_WRAP SINC DINC ERM Reset — Figure 19-9. DCM Parameters Table 19-5 describes DCM bits. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-19...
Page 664 1 CP increments the destination pointer (D_PTR) with the number of bytes transferred in the destination write transaction. Used for memory-to-memory and memory-to-peripheral transfers. In fly-by mode, DINC should equal SINC. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-20 Freescale Semiconductor...
Page 665: Data Transfer Types As Programmed In Dcm
On the bus: one burst or more, depends on STS SS_MAX or Write to memory: in one transfer or more until internal buffer less) empties. On the bus: singles or bursts, depends on DTS MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-21...
Page 666: Programming Dts And Sts
15 * 32 1, 5, 3, 15 31 * 32 31 * 32, 32 1, 31 1024 31 * 32 31 * 32, 32 31 * 32 1, 31 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-22 Freescale Semiconductor...
Page 667: Idma Performance
The transfer parameters STS, DTS, SS_MAX, and DMA_WRAP determine the amount of data transferred for each command issued. Using large internal IDMA transfer buffers and the maximum START IDMA MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-23...
Page 668: Idma Event Register (Idsr) And Mask Register (Idmr)
IDMA BDs. This concept is similar to the one used for the serial controllers on the PowerQUICC II except that the BD is larger because it contains additional information. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-24...
Page 669: Idma Bd Structure
CP until command is issued. START IDMA This bit should be set only in buffer chaining mode (CM bit 6 = 0). — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-25...
Page 670 In fly-by mode, should be the same as DGBL. Source byte ordering: 01 Munged little endian 1x Big endian (Freescale) 00 Reserved In fly-by mode, should be the same as DBO. — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-26 Freescale Semiconductor...
Page 671: Idma Commands
The channel has finished a transfer of a BD with the last bit (L) set. If the command is reissued and channel has more buffers to transfer, it restarts transferring START IDMA data according to the next BD in the buffer table. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-27...
Page 672: Idma Bus Exceptions
TEA to detect a bus exception for the current bus transaction. TEA terminates the transaction immediately and negates DACK, which is used to control the transfer to/from the device. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-28 Freescale Semiconductor...
Page 673: Externally Recognizing Idma Operand Transfers
PC[0] DACK1 (O) PC[23] — DONE1 (I/O) PC[22] IDMA2 DREQ2 (I) PC[1] DACK2 (O) PC[3] — DONE2 (I/O) PC[2] Table 19-13 describes parallel I/O register programming for port A. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-29...
Page 674: Idma Programming Examples
EDN is set to the core, IDMA channel is stopped. additional DREQ assertions are ignored, until command is issued. START IDMA DCM(S/D) = 10 Peripheral-to-memory mode. DONE DREQ and DACK are connected to the peripheral. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-30 Freescale Semiconductor...
Page 675 DONE assertion by the peripheral: All data in internal buffer is written to memory in one transfer. At the end of the transfer, EDN interrupt is set to host. Additional DREQ assertions are ignored. IDMA2 channel is stopped until command is issued. START IDMA MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-31...
Page 676: Memory-To-Peripheral Fly-By Mode—Idma3
IDMA3 configuration: DREQ is level high. DONE is high to low. request priority is higher than the SCCs. 89FE = 0x0300 IDMA3_BASE points to 0x0300 where the parameter table base address is located for IDMA3. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-32 Freescale Semiconductor...
Page 677: Memory-To-Memory (Pci Bus To 60X Bus)—Idma1
DCM[DT] = DC. Do not care. DONE assertion is not defined in memory-to-memory mode. DCM[S/D] = 00 Memory-to-memory mode. DCM[SINC] = 1 The source memory address is incremented after transfers. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 19-33...
Page 678 : after all data in internal buffer is written to the 60x bus, BD is closed and SC interrupt is set. Channel is STOP IDMA stopped until command is issued. START IDMA MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 19-34 Freescale Semiconductor...
Page 679 Using NMSI, an SCC can support standard modem interface signals, RTS, CTS, and CD. If required, software and additional parallel I/O lines can be used to support additional handshake signals. Figure 20-1 shows the SCC block diagram. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 20-1...
Page 680: Scc Block Diagram
Transmit-on-demand feature decreases time to frame transmission (transmit latency) • Low FIFO latency option for send and receive in character-oriented and totally transparent protocols • Frame preamble options • Full-duplex operation MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 20-2 Freescale Semiconductor...
Page 681: The General Scc Mode Registers (Gsmr1–Gsmr4)
1 Reverses the bit order for totally transparent channels on this SCC (either the receiver, transmitter, or both) and sends the msb of each byte first. Section 23.11, “BISYNC Mode Register (PSMR),” describes reversing bit order in a BISYNC protocol. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 20-3...
Page 682 CTS is asserted to the SCC. Assuming CTS is asserted, transmission begins 8 clocks after the receiver starts receiving data. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 20-4 Freescale Semiconductor...
Page 683: Gsmr_L—General Scc Mode Register (Low Order)
0x11A02 (SCC1); 0x11A22 (SCC2); 0x11A42 (SCC3); 0x11A62 (SCC4) Figure 20-3. GSMR_L—General SCC Mode Register (Low Order) Table 20-2 describes GSMR_L fields. Table 20-2. GSMR_L Field Descriptions Name Description — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 20-5...
Page 684 010 16 bits (2 bytes). 011 32 bits (4 bytes). 100 48 bits (6 bytes). Select this setting for Ethernet operation. 101 64 bits (8 bytes). 110 128 bits (16 bytes). 111 Reserved. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 20-6 Freescale Semiconductor...
Page 685 001 NRZI Mark (set RINV/TINV also for NRZI space). 010 FM0 (set RINV/TINV also for FM1). 011 Reserved. 100 Manchester. 101 Reserved. 110 Differential Manchester (Differential Bi-phase-L). 111 Reserved. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 20-7...
Page 686 STOP TRANSMIT GRACEFUL STOP TRANSMIT RESTART TRANSMIT and CTS flow control option in UART mode, and the R bit of the TxBD, also provide the capability to control the transmitter. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 20-8 Freescale Semiconductor...
Page 687: Protocol-Specific Mode Register (Psmr)
HDLC—At reset, DSR defaults to 0x7E7E (two HDLC flags), so it does not need to be written. Figure 20-4 shows the sync fields. Field SYN2 SYN1 Reset 0111_1110 0111_1110 Addr 0x0x11A0E (DSR1); 0x0x11A2E (DSR2); 0x0x11A4E (DSR3); 0x0x11A6E (DSR4) Figure 20-4. Data Synchronization Register (DSR) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 20-9...
Page 688: Transmit-On-Demand Register (Todr)
These bits vary from protocol to protocol. The CPM updates the status bits after the buffer is sent or received. • The half word at offset + 0x2 (data length) holds the number of bytes sent or received. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 20-10 Freescale Semiconductor...
Page 689: Scc Buffer Descriptors (Bds)
Figure 20-7 shows the SCC BD table and buffer structure. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 20-11...
Page 690: Scc Bd And Buffer Memory Structure
(CM), E remains set. When the CPM discovers a descriptor’s W bit set (indicating it is the last BD in the circular BD table), it returns to the beginning of the table when it is time to move to the next buffer. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 20-12...
Page 691: Scc Parameter Ram
Changing MRBLR has no immediate effect. To guarantee the exact Rx BD on which the change occurs, change MRBLR only while the receiver is disabled. Transmit buffer length is programmed in TxBD[Data Length] and is not affected by MRBLR. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 20-13...
Page 692: Scc Base Addresses
The exact definition of the parameter RAM is contained in each protocol subsection describing a device that uses a parameter RAM. For example, the Ethernet parameter RAM is defined differently in some locations from the HDLC-specific parameter RAM. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 20-14 Freescale Semiconductor...
Page 693: Function Code Registers (Rfcr And Tfcr)
TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access. Data bus indicator 0 Use 60x bus for SDMA operation 1 Use local bus for SDMA operation — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 20-15...
Page 694: Handling Scc Interrupts
RxBD. A common practice is to process all RxBDs in the interrupt handler until one is found with RxBD[E] set. 4. Execute the rfi instruction. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 20-16 Freescale Semiconductor...
Page 695: Initializing The Sccs
CTS is already asserted to the SCC or that CTS is reprogrammed to be a parallel I/O line, in which case CTS to the SCC is always asserted. RTS is negated one clock after the last bit in the frame. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 20-17...
Page 696: Output Delay From Rts Asserted For Synchronous Protocols
Negating CTS forces RTS high and Tx data to become idle. If GSMR_H[CTSS] is zero, the SCC must sample CTS before a CTS lost is recognized; otherwise, the negation of CTS immediately causes the CTS lost condition. See Figure 20-11. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 20-18 Freescale Semiconductor...
Page 697: Cts Lost In Synchronous Protocols
20-12. If GSMR_H[CDS] is zero, CD is sampled on the rising Rx clock edge before data is received. If GSMR_H[CDS] is 1, CD transitions cause data to be immediately gated into the receiver. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 20-19...
Page 698: Asynchronous Protocols
If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 0, transmission begins in three additional bit times. • If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 1, transmission begins in two additional bit times. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 20-20 Freescale Semiconductor...
Page 699: Digital Phase-Locked Loop (Dpll) Operation
Carrier SNC EDGE DPLL TSNC Noise Receiver Hunting RINV 1x Mode Decoded Data HSRCLK RINV SCCR Data RENC = NRZI 1x Mode HSRCLK Figure 20-13. DPLL Receiver Block Diagram MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 20-21...
Page 700: Dpll Transmitter Block Diagram
GSMR_L[TPP, TPL]. Table 20-8. Preamble Requirements Decoding Method Preamble Pattern Minimum Preamble Length Required NRZI Mark All zeros 8-bit NRZI Space All ones 8-bit All ones 8-bit MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 20-22 Freescale Semiconductor...
Page 701: Encoding Data With A Dpll
NRZI Mark, NRZI Space, FM0, FM1, Manchester, and Differential Manchester. Figure 20-15 shows the different encoding methods. Data NRZI Mark NRZI Space Manchester Differential Manchester Figure 20-15. DPLL Encoding Examples MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 20-23...
Page 702: Reconfiguring The Sccs
2. Clear GSMR_L[ENT] to disable the SCC transmitter and put it in reset state. 3. Modify SCC Tx parameters or parameter RAM. To switch protocols or restore the initial Tx parameters, issue an command. INIT TX PARAMETERS MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 20-24 Freescale Semiconductor...
Page 703: Reset Sequence For An Scc Transmitter
3. Set GSMR_L[ENT, ENR] to enable the SCC with the new protocol. 20.3.8 Saving Power To save power when not in use, an SCC can be disabled by clearing GSMR_L[ENT, ENR]. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 20-25...
Page 704 Serial Communications Controllers (SCCs) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 20-26 Freescale Semiconductor...
Page 705: Uart Character Format
In multidrop mode, frames of characters are broadcast with the first character acting as a destination address. To accommodate this, the UART frame is extended one bit to distinguish address characters from normal data characters. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 21-1...
Page 706: Normal Asynchronous Mode
UART mode register (PSMR) define the length and format of the UART character. Bits are received in the following order: 1. Start bit 2. 5–8 data bits (lsb first) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 21-2 Freescale Semiconductor...
Page 707: Synchronous Mode
21.4 SCC UART Parameter RAM For UART mode, the protocol-specific area of the SCC parameter RAM is mapped as in Table 21-1. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 21-3...
Page 708 Hword Control character 1–8. These characters define the Rx control characters on which interrupts can be generated. 0x52 CHARACTER2 Hword 0x54 CHARACTER3 Hword 0x56 CHARACTER4 Hword 0x58 CHARACTER5 Hword 0x5A CHARACTER6 Hword 0x5C CHARACTER7 Hword 0x5E CHARACTER8 Hword MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 21-4 Freescale Semiconductor...
Page 709: Data-Handling Methods: Character- Or Message-Based
Overrun, parity, noise, and framing errors are reported via the BDs and/or error counters in the UART parameter RAM. Signal status is indicated in the status register; a maskable interrupt is generated when status changes. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 21-5...
Page 710: Scc Uart Commands
The UART frame is extended by one bit to distinguish an address character from standard data characters. Programmed in PSMR[UM], the controller supports the following two multidrop modes: MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 21-6 Freescale Semiconductor...
Page 711: Receiving Control Characters
The 16-bit entries in the control character table support control character recognition. Each entry consists of the control character, a valid bit (end of table), and a reject bit. See Figure 21-3. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 21-7...
Page 712: Control Character Table
RCCR and generates a maskable interrupt. If the core does not process the interrupt and read RCCR before a new control character arrives, the previous control character is overwritten. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 21-8 Freescale Semiconductor...
Page 713: Hunt Mode (Receiver)
CTS negates when the TOSEQ character is sent. If CTS negates and the TOSEQ character is sent during a buffer transmission, the TxBD[CT] status bit is also set. 5–6 — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 21-9...
Page 714: Sending A Break (Transmitter)
Idle characters are always sent as full-length characters Field — — — — — — — — — — — — Reset 1111 Addr Figure 21-5. Asynchronous UART Transmitter Table 21-6 describes DSR fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 21-10 Freescale Semiconductor...
Page 715: Handling Errors In The Scc Uart Controller
Note that if CTS is used, the UART also offers an asynchronous flow control option that does not generate an error. See the description of PSMR[FLC] in Table 21-9. Reception errors are described in Table 21-8. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 21-11...
Page 716: Uart Mode Register (Psmr)
For UART mode, the SCC protocol-specific mode register (PSMR) is called the UART mode register. Many bits can be modified while the receiver and transmitter are enabled. Figure 21-6 shows the PSMR in UART mode. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 21-12 Freescale Semiconductor...
Page 717: Protocol-Specific Mode Register For Uart (Psmr)
1 The SCC completes transmission of any data already transferred to the Tx FIFO (the number of characters depends on GSMR_H[TFL]) and then freezes. After FRZ is cleared, transmission resumes from the next character. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 21-13...
Page 718: Scc Uart Receive Buffer Descriptor (Rxbd)
A user-defined control character is received. • An error occurs during message processing. • A full receive buffer is detected. • A MAX_IDL number of consecutive idle characters is received. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 21-14 Freescale Semiconductor...
Page 719 An address character is received in multidrop mode. The address character is written to the next buffer for a software comparison. Figure 21-7 shows an example of how RxBDs are used in receiving. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 21-15...
Page 720: Scc Uart Receiving Using Rxbds
Long Idle Period Characters Received by UART Fourth Character Present Time has Framing Error! Time Figure 21-7. SCC UART Receiving using RxBDs Figure 21-8 shows the SCC UART RxBD. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 21-16 Freescale Semiconductor...
Page 721: Scc Uart Receive Buffer Descriptor (Rxbd)
PSMR[UM]. After an address match, AM identifies which user-defined address character was matched. 0 The address matched the value in UADDR2. 1 The address matched the value in UADDR1. — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 21-17...
Page 722: Scc Uart Transmit Buffer Descriptor (Txbd)
RAM. Interrupt. 0 No interrupt is generated after this buffer is processed. 1 SCCE[TX] is set after this buffer is processed by the CPM, which can cause an interrupt. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 21-18 Freescale Semiconductor...
Page 723: Scc Uart Event Register (Scce) And Mask Register (Sccm)
UART mask register (SCCM), which has the same format as SCCE. Setting a mask bit enables the corresponding SCCE interrupt; clearing a bit masks it. Figure 21-10 shows example interrupts that can be generated by the SCC UART controller. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 21-19...
Page 724: Scc Uart Interrupt Event Example
0x0x11A10 (SCCE1); 0x0x11A30 (SCCE2); 0x0x11A50 (SCCE3); 0x0x11A70 (SCCE4) 0x0x11A14 (SCCM1); 0x0x11A34 (SCCM2); 0x0x11A54 (SCCM3); 0x0x11A74 (SCCM4) Figure 21-11. SCC UART Event Register (SCCE) and Mask Register (SCCM) Table 21-12 describes SCCE fields for UART mode. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 21-20 Freescale Semiconductor...
Page 725: Scc Uart Status Register (Sccs)
21-12, monitors the real-time status of RXD. Field — Reset 0000_0000_0000_0000 Addr 0x0x11A17 (SCCS1); 0x0x11A37 (SCCS2); 0x0x11A57 (SCCS3); 0x0x11A77 (SCCS4) Figure 21-12. SCC Status Register for UART Mode (SCCS) Table 21-13 describes UART SCCS fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 21-21...
Page 726: Scc Uart Programming Example
17. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to the RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer]. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 21-22 Freescale Semiconductor...
Page 727: S-Records Loader Application
This buffer contains an entire S record that the processor can now check and copy to memory or disk as required. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 728 XOFF character is received. This scheme minimizes the number of interrupts the core receives (one per S-record) and relieves it from continually scanning for control characters. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 21-24 Freescale Semiconductor...
Page 729: Scc Hdlc Features
Flexible buffers with multiple buffers per frame • Separate interrupts for frames and buffers (Rx and Tx) • Received-frames threshold to reduce interrupt overhead • Can be used with the SCC DPLL MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 22-1...
Page 730: Scc Hdlc Channel Frame Transmission
Once enabled by the core, the receiver waits for an opening flag character. When it detects the first byte of the frame, the SCC compares the frame address with four user-programmable, 16-bit address registers MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 22-2...
Page 731: Scc Hdlc Parameter Ram
BSY condition, but does not include overrun errors. ABTSC (Abort sequence counter) 0x44 RETRC Hword NMARC (Nonmatching address received counter) Includes error-free frames only. RETRC (Frame retransmission counter) Counts number of frames resent due to collision. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 22-3...
Page 732: Programming The Scc In Hdlc Mode
HDLC mode is selected for an SCC by writing GSMR_L[MODE] = 0b0000. The HDLC controller uses the same buffer and BD data structure as other modes and supports multibuffer operation and MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 22-4...
Page 733: Scc Hdlc Commands
Handling Errors in the SCC HDLC Controller The SCC HDLC controller reports frame reception and transmission errors using BDs, error counters, and the SCCE. Transmission errors are described in Table 22-4. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 22-5...
Page 734 CRC error, the receiver enters hunt mode. An immediate back-to-back frame is still received. CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 22-6...
Page 735: Hdlc Mode Register (Psmr)
TCLK and RCLK, and CTS either has synchronous timing or is always asserted. HDLC bus mode. 0 Normal HDLC operation. 1 HDLC bus operation is selected. See Section 22.15, “HDLC Bus Mode with Collision Detection.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 22-7...
Page 736: Scc Hdlc Receive Buffer Descriptor (Rxbd)
RxBD[W] and overall space constraints of the dual-port RAM. Interrupt. 0 SCCE[RXB] is not set after this buffer is used; SCCE[RXF] is unaffected. 1 SCCE[RXB] or SCCE[RXF] is set when the SCC uses this buffer. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 22-8 Freescale Semiconductor...
Page 737 Because HDLC is a frame-based protocol, RxBD[Data Length] of the last buffer of a frame contains the total number of frame bytes, including the 2 or 4 bytes for CRC. Figure 22-5 shows an example of how RxBDs are used in receiving. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 22-9...
Page 738: Scc Hdlc Receiving Using Rxbds
Legend: Closing Flag F = Flag A = Address byte C = Control byte I = Information byte CR = CRC Byte Figure 22-5. SCC HDLC Receiving Using RxBDs MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 22-10 Freescale Semiconductor...
Page 739: Scc Hdlc Transmit Buffer Descriptor (Txbd)
If data from more than one buffer is currently in the FIFO when this error occurs, the HDLC writes CT in the current BD after sending the buffer. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 22-11...
Page 740: Hdlc Event Register (Scce)/Hdlc Mask Register (Sccm)
It is set no sooner than two clocks after the last bit of the closing flag is received. This event is not maskable via the RxBD[I] bit. Busy condition. Indicates a frame arrived but was discarded due to a lack of buffers. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 22-12 Freescale Semiconductor...
Page 741: Scc Hdlc Interrupt Event Example
2. Example shows one additional opening flag. This is programmable. 3. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself. Figure 22-8. SCC HDLC Interrupt Event Example MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 22-13...
Page 742: Scc Hdlc Status Register (Sccs)
1. Configure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear PDIRD[28] and PSORD[27,28]. 2. Configure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26], PPARC[12,13] and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and PSORD[26]. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 22-14 Freescale Semiconductor...
Page 743 HDLC mode. Normal Tx clock operation is used. Notice that the transmitter (ENT) and receiver (ENR) have not been enabled. If inverted HDLC operation is preferred, set RINV and TINV. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 744: Scc Hdlc Programming Example #2
7–10 ones on the echo bit before letting the LAPD frame begin transmission, after which the S/T interface monitors transmitted data. As long as the echo bit matches the sent data, MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 22-16...
Page 745: Typical Hdlc Bus Multimaster Configuration
2. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port. 3. Clock is a common RCLK/TCLK for all stations. Figure 22-10. Typical HDLC Bus Multimaster Configuration MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 22-17...
Page 746: Hdlc Bus Features
(0x7E) while another station is already sending, the collision is always detected within the first byte, because the transmission in progress is using zero bit insertion to prevent flag imitation. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 22-18 Freescale Semiconductor...
Page 747: Increasing Performance
Because it uses a wired-OR configuration, HDLC bus performance is limited by the rise time of the one bit. To increase performance, give the one bit more rise time by using a clock that is low longer than it is high, as shown in Figure 22-13. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 22-19...
Page 748: Delayed Rts Mode
If the transmission line driver has a one-bit delay, the delayed RTS can be used to enable the output of the line driver. As a result, the electrical effects of collisions are isolated locally. Figure 22-15 shows RTS timing. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 22-20 Freescale Semiconductor...
Page 749: Using The Time-Slot Assigner (Tsa)
Because collisions are still detected from the individual SCC CTS pin, it must be configured to connect to the chosen SCC. Because the SCC only receives clocks during its time slot, CTS is sampled only during the Tx clock edges of the particular SCC time slot. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 22-21...
Page 750: Hdlc Bus Protocol Programming
22.15.6.2 HDLC Bus Controller Programming Example Except for the above discussion in Section 22.15.6.1, “Programming GSMR and PSMR for the HDLC Bus Protocol,” use the example in Section 22.14, “SCC HDLC Programming Example #1.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 22-22 Freescale Semiconductor...
Page 751: Classes Of Bisync Frames
The controller can work with the time-slot assigner (TSA) or nonmultiplexed serial interface (NMSI). The controller has separate transmit and receive sections whose operations are asynchronous with the core and either synchronous or asynchronous with other SCCs. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 23-1...
Page 752: Scc Bisync Channel Frame Transmission
The controller can reset the BCS generator before sending a specific buffer. In transparent mode, the controller inserts a DLE before sending a DLE character, so that only one DLE is used in the calculation. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 23-2 Freescale Semiconductor...
Page 753: Scc Bisync Channel Frame Reception
DLE–SYNC pair in an underrun condition and stripped from incoming data on receive once the receiver synchronizes to the data using the DSR and SYN1–SYN2 pair. See Section 23.7, “BISYNC SYNC Register (BSYNC).” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 23-3...
Page 754: Scc Bisync Commands
23.5 SCC BISYNC Commands Transmit and receive commands are issued to the CP command register (CPCR). Transmit commands are described in Table 23-2. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 23-4 Freescale Semiconductor...
Page 755: Scc Bisync Control Character Recognition
BISYNC controller and aid its operation in a DMA-oriented environment. They are used for receive buffers longer than one byte. In single-byte buffers, each byte can be easily inspected so control character recognition should be disabled. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 23-5...
Page 756: Control Character Table And Rccm
0x4D — CHARACTER6 0x4E — CHARACTER7 0x50 — CHARACTER8 0x52 — MASK VALUE(RCCM) Figure 23-2. Control Character Table and RCCM Table 23-4 describes control character table and RCCM fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 23-6 Freescale Semiconductor...
Page 757: Bisync Sync Register (Bsync)
SYNC register value. Field SYNC Reset Undefined Addr SCC Base + 0x3E Figure 23-3. BISYNC SYNC (BSYNC) Table 23-5 describes BSYNC fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 23-7...
Page 758: Scc Bisync Dle Register (Bdle)
When using 7-bit characters with parity, the parity bit should be included in the DLE register value. Field Reset Undefined Addr SCC Base + 0x40 Figure 23-4. BISYNC DLE (BDLE) Table 23-6 describes BDLE fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 23-8 Freescale Semiconductor...
Page 759: Sending And Receiving The Synchronization Sequence
The controller reports message transmit and receive errors using the channel BDs, error counters, and the SCCE. Modem lines can be directly monitored via the parallel port pins. Table 23-8 describes transmit errors. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 23-9...
Page 760: Bisync Mode Register (Psmr)
Field RBCS RTR RVD DRT — Reset Addr 0x0x11A08 (PSMR1); 0x0x11A28 (PSMR2); 0x0x11A48 (PSMR3); 0x0x11A68 (PSMR4) Figure 23-5. Protocol-Specific Mode Register for BISYNC (PSMR) Table 23-10 describes PSMR fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 23-10 Freescale Semiconductor...
Page 761 Note: If DRT = 1, GSMR_H[CDS] should be cleared unless both of the following are true: the same clock is used for TCLK and RCLK, and CTS either has synchronous timing or is always asserted. 10–11 — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 23-11...
Page 762: Scc Bisync Receive Bd (Rxbd)
RxBD. The CP does not use this BD as long as the E bit is zero. 1 The buffer is not full. The CP controls this BD and buffer. The core should not update this BD. — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 23-12 Freescale Semiconductor...
Page 763 CP writes into this buffer, including the BCS. For BISYNC mode, clear these bits. It is incremented each time a received character is written to the buffer. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 764: Scc Bisync Transmit Bd (Txbd)
1 The CP does not clear R after this BD is closed, so the buffer is resent when the CP next accesses this BD. However, R is cleared if an error occurs during transmission, regardless of how CM is set. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 23-14 Freescale Semiconductor...
Page 765: Bisync Event Register (Scce)/Bisync Mask Register (Sccm)
(SCCM). SCCE bits are reset by writing ones; writing zeros has no effect. Unmasked bits must be reset before the CP negates the internal interrupt request signal. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 23-15...
Page 766: Scc Status Registers (Sccs)
CTS and CD are part of the parallel I/O. Field — — Reset 0000_0000 Addr 0x0x11A17 (SCCS1); 0x0x11A37 (SCCS2); 0x0x11A57 (SCCS3); 0x0x11A77 (SCCS4) Figure 23-9. SCC Status Registers (SCCS) Table 23-14 describes SCCS fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 23-16 Freescale Semiconductor...
Page 767: Programming The Scc Bisync Controller
Using Table 23-15, the control character table should be set to recognize the end of the block. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 23-17...
Page 768: Scc Bisync Programming Example
13. Write BSYNC with 0x8033, assuming a SYNC value of 0x33. 14. Write DSR with 0x3333. 15. Write BDLE with 0x8055, assuming a DLE value of 0x55. 16. Write CHARACTER1 with 0x6077, assuming ETX = 0x77. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 23-18 Freescale Semiconductor...
Page 769 ENT and ENR are enabled last. After 5 bytes are sent, the TxBD is closed. The buffer is closed after 16 bytes are received. Any received data beyond 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 23-19...
Page 770 SCC BISYNC Mode MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 23-20 Freescale Semiconductor...
Page 771: Features
Automatic SYNC detection on receive • CRCs can be sent and received • Reverse data mode • Another protocol can be performed on the other half of the SCC • MC68360-compatible SYNC options MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 24-1...
Page 772: Scc Transparent Channel Frame Transmission Process
The receiver always checks the CRC of the received frame, according to GSMR_H[TCRC]. If a CRC is not required, resulting errors can be ignored. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 24-2 Freescale Semiconductor...
Page 773: Achieving Synchronization In Transparent Mode
GSMR_H[CDP] and GSMR_H[CTSP] determine whether CD or CTS need to be asserted only once to begin reception/transmission or whether they must remain asserted for the duration of the transparent MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 24-3...
Page 774: External Synchronization Example
RTS and CD. However, CTS is not required because transmission begins at any time. Thus, RTS is connected directly to the other PowerQUICC II CD pin. GSMR_H[RSYN] is not used and transmission and reception from each PowerQUICC II are independent. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 24-4 Freescale Semiconductor...
Page 775: Transparent Mode Without Explicit Synchronization
An end of frame cannot be detected in the transparent data stream since there is no defined closing flag in transparent mode. Therefore, if framing is needed, the user must use the CD line to alert the transparent controller of an end of frame. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 24-5...
Page 776: Crc Calculation In Transparent Mode
The current TxBD pointer (TBPTR) advances to the next TxBD in the table. Transmission resumes once TxBD[R] is set and a command is issued. RESTART TRANSMIT MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 24-6 Freescale Semiconductor...
Page 777: Handling Errors In The Transparent Controller
When this occurs, the channel stops sending the buffer, closes it, sets TxBD[CT], and generates the Message TXE interrupt if it is enabled. The channel resumes sending after is received. RESTART TRANSMIT Transmission Table 24-6 describes receive errors. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 24-7...
Page 778: Transparent Mode And The Psmr
Offset + 2 Data Length Offset + 4 Rx Buffer Pointer Offset + 6 Figure 24-2. SCC Transparent Receive Buffer Descriptor (RxBD) Table 24-7 describes RxBD status and control fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 24-8 Freescale Semiconductor...
Page 779 CRC checking cannot be disabled, but it can be ignored. Overrun. Indicates that a receiver overrun occurred during buffer reception. Carrier detect lost. Indicates when CD is negated during buffer reception. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 24-9...
Page 780: Scc Transparent Transmit Buffer Descriptor (Txbd)
Transmit CRC. 0 No CRC sequence is sent after this buffer. 1 A frame check sequence defined by GSMR_H[TCRC] is sent after the last byte of this buffer. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 24-10 Freescale Semiconductor...
Page 781: Scc Transparent Event Register (Scce)/Mask Register (Sccm)
DPLL is used). Real-time status can be read in SCCS. This is not the CD status mentioned elsewhere. 6–7 — Reserved, should be cleared. Refer to note 1 below. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 24-11...
Page 782: Scc Status Register In Transparent Mode (Sccs)
24.14 SCC2 Transparent Programming Example The following initialization sequence enables the transmitter and receiver, which operate independently of each other. They implement the connection shown on PowerQUICC II(B) in Figure 24-1. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 24-12 Freescale Semiconductor...
Page 783 (ENT) and receiver (ENR) are not enabled yet. 20. Write 0x0000_0030 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional write ensures that the ENT and ENR bits are enabled last. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 24-13...
Page 784 After 5 bytes are sent, the Tx buffer is closed and after 16 bytes are received the Rx buffer is closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 24-14 Freescale Semiconductor...
Page 785: Ethernet On The Powerquicc Ii
25.1 Ethernet on the PowerQUICC II Setting GSMR[MODE] to 0b1100 selects Ethernet. The SCC performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 25-1...
Page 786: Ethernet Block Diagram
— Automatically pads short frames on transmit — Framing error (dribbling bits) handling • Full collision support — Enforces the collision (jamming) — Truncated binary exponential backoff algorithm for random wait MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 25-2 Freescale Semiconductor...
Page 787 — Busy (out of buffers) • Error counters — Discarded frames (out of buffers or overrun occurred) — CRC errors — Alignment errors • Internal and external loopback mode MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 25-3...
Page 788: Connecting The Powerquicc Ii To Ethernet
PowerQUICC II can perform external loopback testing, which can be controlled by any available PowerQUICC II parallel I/O signal. The passive components needed to MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 25-4 Freescale Semiconductor...
Page 789: Scc Ethernet Channel Frame Transmission
When the Ethernet controller receives a command, it resumes transmission. The Ethernet controller sends bytes RESTART TRANSMIT least-significant bit first. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 25-5...
Page 790: Scc Ethernet Channel Frame Reception
This signal is asserted for one bit time on the second destination address bit. The CAM control logic uses RSTRT (in combination with the RXD and RCLK signals) to store the destination or source address and MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 25-6...
Page 791: Scc Ethernet Parameter Ram
The controller reports frame status and length in the last BD. MFLR is defined as all in-frame bytes between the start frame delimiter and the end of the frame. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 25-7...
Page 792 LAN increases overall throughput by reducing the chance of collision. PSMR[SBT] offers another way to reduce the aggressiveness of the Ethernet controller. 0x7A RFBD_PTR Hword Rx first BD pointer. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 25-8 Freescale Semiconductor...
Page 793: Programming The Ethernet Controller
(including the 1-byte start delimiter with the value 0xD5). 25.9 SCC Ethernet Commands Transmit and receive commands are issued to the CP command register (CPCR). Table 25-2 describes transmit commands. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 25-9...
Page 794: Programming Example
RTS, active-low functionality. To prevent false TENA assertions to an external transceiver, configure TENA as an input before issuing a CPM reset. See step 3 in Section 25.21, “SCC Ethernet Programming Example.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 25-10 Freescale Semiconductor...
Page 795: Scc Ethernet Address Recognition
In group address recognition, the controller determines whether the group address is a broadcast address. If broadcast addresses are enabled, the frame is accepted, but if the group address is not a broadcast MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 796: Hash Table Algorithm
If a collision occurs as a frame is being sent, the Ethernet controller continues sending for at least 32 bit times, thus sending a JAM pattern of 32 ones. If a collision occurs during the preamble sequence, the JAM pattern is sent at the end of the sequence. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 25-12 Freescale Semiconductor...
Page 797: Internal And External Loopback
The channel stops sending the buffer, closes it, sets the RL bit in the TxBD and SCCE[TXE]. attempts limit expired The channel resumes transmission after it receives a command. RESTART TRANSMIT MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 25-13...
Page 798: Ethernet Mode Register (Psmr)
Ethernet mode register. Field HBC PRO BRO SBT — Reset 0000_0000_0000_0000 Addr 0x0x11A08 (PSMR1); 0x0x11A28 (PSMR2); 0x0x11A48 (PSMR3); 0x0x11A68 (PSMR4) Figure 25-5. Ethernet Mode Register (PSMR) Table 25-6 describes PSMR fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 25-14 Freescale Semiconductor...
Page 799 0 A late collision is any collision that occurs at least 64 bytes from the preamble. 1 A late collision is any collision that occurs at least 56 bytes from the preamble. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 800: Scc Ethernet Receive Bd
0 No SCCE[RXB] interrupt is generated after this buffer is used. 1 SCCE[RXB] or SCCE[RXF] is set when this buffer is used by the Ethernet controller. These two bits can cause interrupts if they are enabled. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 25-16 Freescale Semiconductor...
Page 801 Section 20.2, “SCC Buffer Descriptors (BDs).” Data length includes the total number of frame octets (including four bytes for CRC). Figure 25-7 shows an example of how RxBDs are used in receiving. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 25-17...
Page 802: Scc Ethernet Transmit Buffer Descriptor
TxBD table. The Ethernet controller uses TxBDs to confirm transmission or indicate errors so the core knows buffers have been serviced. Figure 25-8 represents an SCC ethernet transmit buffer descriptor. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 25-18 Freescale Semiconductor...
Page 803: Scc Ethernet Txbd
Retransmission limit. Set when the transmitter fails (Retry Limit + 1) attempts to successfully transmit a message because of repeated collisions on the medium. The Ethernet controller writes this bit after it finishes attempting to send the buffer. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 25-19...
Page 804: Scc Ethernet Event Register (Scce)/Mask Register (Sccm)
Rx frame. Set when a complete frame has been received on the Ethernet channel. Busy condition. Set when a frame is received and discarded due to a lack of buffers. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 25-20 Freescale Semiconductor...
Page 805: Ethernet Interrupt Events Example
Note that the SCC status register (SCCS) cannot be used with the Ethernet protocol. The current state of the RENA and CLSN signals can be found in the parallel I/O ports. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 806: Scc Ethernet Programming Example
TxBD[Data Length] and 0x0000_2000 to TxBD[Buffer Pointer]. 21. Write 0xFFFF to the SCCE register to clear any previous events. 22. Write 0x001A to the SCCM register to enable the TXE, RXF, and TXB interrupts. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 25-22 Freescale Semiconductor...
Page 807 Additionally, the receive buffer is closed after a frame is received. Any data received after 1520 bytes or a single frame causes a busy (out-of-buffers) condition because only one RxBD is prepared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 808 SCC Ethernet Mode MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 25-24 Freescale Semiconductor...
Page 809: Operating The Localtalk Bus
Frames are sent in groups known as dialogs, which are handled by the software. For instance, to transfer a data frame, three frames are sent over the network. An RTS frame (not to be confused with the RS-232 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 810: Connecting To Appletalk
RS-422 transceiver. The RS-422, in turn, is an interface for the LocalTalk connector. Although it is not shown, a passive RC circuit is recommended between the transceiver and connector. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 26-2...
Page 811: Programming The Scc In Appletalk Mode
LocalTalk synchronization sequence. For example, data frames do not require a preceding synchronization sequence. These bits may be modified on-the-fly if the AppleTalk protocol is selected. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 26-3...
Page 812: Programming The Psmr
Use the transmit-on-demand (TODR) register to expedite a transmit frame. See Section 20.1.4, “Transmit-on-Demand Register (TODR).” 26.4.4 SCC AppleTalk Programming Example Except for the previously discussed register programming, use the example in Section 22.15.6, “HDLC Bus Protocol Programming.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 26-4 Freescale Semiconductor...
Page 813: Smc Block Diagram
GCI interface configuration. Figure 27-1 shows the SMC block diagram. 60x Bus SYNC Control Control Registers Logic Peripheral Bus Data Data Register Register Shifter Shifter Figure 27-1. SMC Block Diagram MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-1...
Page 814: Common Smc Settings And Configurations
27-2, selects the SMC mode as well as mode-specific parameters. The functions of SMCMR[8–15] are the same for each protocol. Bits 0–7 vary according to protocol selected by the SM bits. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-2 Freescale Semiconductor...
Page 815: Smc Mode Registers (Smcmr1/Smcmr2)
1 Two stop bits. — Reserved, should be cleared. (transparent) Monitor enable. (GCI) 0 The SMC does not support the monitor channel. 1 The SMC supports the monitor channel. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-3...
Page 816: Smc Buffer Descriptor Operation
In UART and transparent modes, the SMC’s memory structure is like the SCC’s, except that SMC-associated data is stored in buffers. Each buffer is referenced by a BD and organized in a BD table located in the dual-port RAM. See Figure 27-3. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-4 Freescale Semiconductor...
Page 817: Smc Parameter Ram
The protocol-specific portions of the SMC parameter RAM are discussed in the sections that follow. The SMC parameter RAM shared by the UART and transparent protocols is shown in Table 27-2. Parameter RAM for GCI protocol is described in Table 27-17. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-5...
Page 818 GRACEFUL STOP TRANSMIT transmission. 0x22 — Hword Tx internal byte count. A down-count value initialized with the TxBD data length and decremented with every byte the SDMA channels read. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-6 Freescale Semiconductor...
Page 819 Values for the SMC receiver can be written only when SMCMR[REN] is zero, or, if the receiver is previously enabled, after an command is issued but before the ENTER HUNT MODE CLOSE RXBD command is issued and REN is set. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-7...
Page 820: Smc Function Code Registers (Rfcr/Tfcr)
RAM values can be modified. To disable all SCCs, SMCs, the SPI, and the I C, use the CPCR to reset the CPM with a single command. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-8 Freescale Semiconductor...
Page 821: Smc Transmitter Full Sequence
To switch the protocol that the SMC is executing without resetting the board or affecting any other SMC, use one command and follow these steps: 1. Clear SMCMR[REN] and SMCMR[TEN]. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-9...
Page 822: Saving Power
(not to scale) SMTXD Start 5 to 14 Data Bits with the Parity 1 or 2 Least Significant Bit First Stop Bits (Optional) Figure 27-5. SMC UART Frame Format MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-10 Freescale Semiconductor...
Page 823: Smc Uart Channel Transmission Process
(SMCMR1/SMCMR2).” UART mode uses the same data structure as other modes. This structure supports multibuffer operation and allows break and preamble sequences to be sent. Overrun, parity, and framing MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-11...
Page 824: Smc Uart Transmit And Receive Commands
SMC sends a character of consecutive zeros, the number of which is the sum of the character length, plus the number of start, parity, and stop bits. The SMC sends a programmable MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-12...
Page 825: Sending A Preamble
• An error is received during message processing • A full receive buffer is detected MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-13...
Page 826: Smc Uart Rxbd
A framing error is a character with no stop bit. A new receive buffer is used to receive additional data. The CP writes FR after the received data is in the buffer. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-14...
Page 827 UART RxBD process, showing RxBDs after they receive 10 characters, an idle period, and five characters (one with a framing error). The example assumes that MRBLR = 8. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-15...
Page 828: Rxbd Example
Still in Progress (MAX_IDL) with this Buffer 10 Characters 5 Characters Long Idle Period Characters Received by UART Fourth Character Present Time has Framing Error! Time Figure 27-7. RxBD Example MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-16 Freescale Semiconductor...
Page 829: Smc Uart Txbd
If there are more than 8 bits in the UART character, data length should be even. For example, to transmit three UART characters of 8-bit data, 1 start, and 1 stop, initialize the data length field MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 830: Smc Uart Event Register (Smce)/Mask Register (Smcm)
Figure 27-10 shows an example of the timing of various events in the SMCE. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-18 Freescale Semiconductor...
Page 831: Smc Uart Controller Programming Example
MAX_IDL functionality for this example. 10. Clear BRKLN and BRKEC in the SMC UART-specific parameter RAM. 11. Set BRKCR to 0x0001; if a is issued, one break character is sent. STOP TRANSMIT COMMAND MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-19...
Page 832: Smc In Transparent Mode
Features The following list summarizes the features of the SMC in transparent mode: • Flexible data buffers • Connects to a TDM bus using the TSA in an SIx MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-20 Freescale Semiconductor...
Page 833: Smc Transparent Channel Transmission Process
When the buffer full, the SMC clears the E bit in the BD and generates an interrupt if the I bit in the BD is set. If incoming data exceeds the data buffer length, the SMC fetches the next BD; if it is empty, the MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 834: Using Smsyn For Synchronization
Glitches on SMSYN can cause errant behavior of the SMC. The transmitter never loses synchronization again, regardless of the state of SMSYN, until the TEN bit is cleared or an command is issued. ENTER HUNT MODE MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-22 Freescale Semiconductor...
Page 835: Using The Time-Slot Assigner (Tsa) For Synchronization
The TSA allows the SMC receiver and transmitter to be enabled simultaneously and synchronized separately; SMSYN does not provide this capability. Figure 27-12 shows synchronization using the TSA. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-23...
Page 836: Synchronization With The Tsa
TxBD is always ready and that underruns do not occur. Otherwise, the SMC transmitter should be disabled and reenabled. Section 27.2.4, “Disabling SMCs On-the-Fly,” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-24 Freescale Semiconductor...
Page 837: Smc Transparent Commands
PARAMETERS INIT TX AND RX PARAMETERS 27.4.7 Handling Errors in the SMC Transparent Controller The SMC uses BDs and the SMCE to report message send and receive errors. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-25...
Page 838: Smc Transparent Rxbd
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that RBASE points to. The number of RxBDs is determined only by the W bit and overall space constraints of the dual-port RAM. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-26 Freescale Semiconductor...
Page 839: Smc Transparent Txbd
1 The user-prepared data buffer is not sent or is being sent. BD fields cannot be updated if R is set. — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-27...
Page 840: Smc Transparent Event Register (Smce)/Mask Register (Smcm)
SMCM, which has the same format as the SMCE. SMCE bits are cleared by writing a 1 (writing 0 has no effect). Unmasked bits must be cleared before the CP clears the internal interrupt request. The SMCE and SMCM registers are displayed in Figure 27-14. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-28 Freescale Semiconductor...
Page 841: Smc Transparent Nmsi Programming Example
TxBD, write RBASE with 0x0000 and TBASE with 0x0008. 6. Write 0x1D01_0000 to CPCR to execute the command. INIT RX AND TX PARAMETERS 7. Write RFCR and TFCR with 0x10 for normal operation. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-29...
Page 842: The Smc In Gci Mode
RAM contains the BDs instead of pointers to them. Compare Table 27-17 with Table 27-2 on page 27-6 to see the differences. (In GCI mode, the SMC has no extra protocol-specific parameter RAM.) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-30 Freescale Semiconductor...
Page 843: Handling The Gci Monitor Channel
When the CP stores a received data byte in the SMC RxBD, a maskable interrupt is generated. command causes the PowerQUICC II to send an abort request on the E bit. TRANSMIT ABORT REQUEST MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-31...
Page 844: Handling The Gci C/I Channel
27-15, is used by the CP to report information about the monitor channel receive byte. Offset + 0 — DATA Figure 27-15. SMC Monitor Channel RxBD Table 27-19 describes SMC monitor channel RxBD fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-32 Freescale Semiconductor...
Page 845: Smc Gci Monitor Channel Txbd
Data field. Contains the data to be sent by the SMC on the monitor channel. 27.5.7 SMC GCI C/I Channel RxBD The CP uses this BD, seen in Figure 27-17, to report information about the C/I channel receive byte. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-33...
Page 846: Smc Gci C/I Channel Txbd
SMCM has the same bit format as SMCE. Setting an SMCM bit enables, and clearing an SMCM bit disables, the corresponding interrupt. Unmasked bits must be cleared before the CP clears MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-34...
Page 847: Smc Gci Event Register (Smce)/Mask Register (Smcm)
CRXB C/I channel buffer received. Set when the C/I receive buffer is full. MTXB Monitor channel buffer transmitted. Set when the monitor transmit buffer is now empty. MRXB Monitor channel buffer received. Set when the monitor receive buffer is full. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 27-35...
Page 848 Serial Management Controllers (SMCs) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 27-36 Freescale Semiconductor...
Page 849 • Global loop mode • Individual channel loop mode • Efficient bus usage (no bus usage for inactive channel or for active channels with nothing to transmit) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-1...
Page 850: Mcc Operation Overview
128*CH_NUM. CH_NUM is the channel number (0–127 for MCC1 and 128–255 for MCC2). Channel-specific parameters are described in the following sections: — Section 28.3.1, “Channel-Specific HDLC Parameters” — Section 28.3.2, “Channel-Specific Transparent Parameters” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-2 Freescale Semiconductor...
Page 851: Bd Structure For One Mcc
Channel 1 Parameter Channel j Extra RBASE Channel j RxBD Parameter TBASE 512 Kbytes Table Global MCC MCCBASE Parameters Channel j TxBD Table Figure 28-1. BD Structure for One MCC MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-3...
Page 852: Global Mcc Parameters
60x initializes this field before initializing the MCC. The user must clear it before enabling interrupts. 0x24 SCTPBASE Hword Internal pointer for the super channel transmit table, offset from the DPRAM address 0x26 — Hword MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-4 Freescale Semiconductor...
Page 853: Channel-Specific Parameters
The following sections describe the various programming models used for an MCC channel. 28.3.1 Channel-Specific HDLC Parameters Table 28-2 describes channel-specific parameters for HDLC. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-5...
Page 854 RBDCNT Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only for the user) 0x34 RBDPTR Word Rx internal data pointer. Points to current absolute data address of channel, used by the CP (read-only for the user) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-6 Freescale Semiconductor...
Page 855: Internal Transmitter State (Tstate)—Hdlc Mode
Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 856: Channel Mode Register (Chamr)—Hdlc Mode
Section 28.3.3.2, “Channel Mode Register (CHAMR)—AAL1 CES,” for additional information. Field MODE POL IDLM — — — Reset — Offset 0x1A Figure 28-4. Channel Mode Register (CHAMR) CHAMR fields are described in Table 28-4. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-8 Freescale Semiconductor...
Page 857 Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*n-4 (n is any integer larger than 0). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-9...
Page 858: Internal Receiver State (Rstate)—Hdlc Mode
Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-10...
Page 859: Channel-Specific Transparent Parameters
Word Rx internal state. To start a receiver channel the user must write to RSTATE 0xHH80_0000. HH is the RSTATE high byte described in Section 28.3.1.4, “Internal Receiver State (RSTATE)—HDLC Mode.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-11...
Page 860: Interrupt Mask (Intmsk)—Transparent Mode
In transparent mode, TSTATE functions the same as in HDLC mode. For a description, refer to Section 28.3.1.1. 28.3.2.2 Interrupt Mask (INTMSK)—Transparent Mode In transparent mode, INTMSK functions the same as in HDLC mode. For a description, refer to Section 28.3.2.2. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-12 Freescale Semiconductor...
Page 861: Channel Mode Register (Chamr)—Transparent Mode
1 The E bit in the RxBD is handled in negative logic (0 = empty, 1 = not empty). Polling occurs disregarding the value of POL. 0 Normal bit order (transmit/receive the lsb of each octet first) 1 Reversed bit order (transmit/receive the msb of each octet first) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-13...
Page 862: Internal Receiver State (Rstate)—Transparent Mode
When using AAL1 CES, the structured and unstructured data are transferred between the ATM and MCC automatically without CPU intervention. Refer to Chapter 31, “ATM AAL1 Circuit Emulation Service.” The following subsections describe the additional parameters required for AAL1 CES. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-14 Freescale Semiconductor...
Page 863: Channel-Specific Parameters—Aal1 Ces
Figure 28-6 shows the user-initialized channel mode register, CHAMR, for CES operation. It is the same as the CHAMR in transparent mode with three extra CES fields in bits 13–15. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-15...
Page 864: Channel Mode Register (Chamr)—Ces Mode
The second byte of the sync pattern will be written to the receive buffer (first and second represent the order in which the two bytes of the sync pattern are received on the serial channel). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-16 Freescale Semiconductor...
Page 865: Channel-Specific Ss7 Parameters
Initial alignment (supports alignment error rate monitoring) Host software, however, is needed to handle the following higher-level functions of the MTP layer 2 not supported by the SS7 controller: • Link state control MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-17...
Page 866 Uses 64-bit data transactions for reading and writing data in BDs Table 28-10 describes channel-specific parameters for SS7. Note that a given parameter location may have a different definition depending on the standard used (ITU-T/ANSI or Japanese standard). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-18 Freescale Semiconductor...
Page 867 Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only for the user) 0x34 RBDPTR Word Rx internal data pointer. Points to current absolute data address of channel, used by the CP (read-only for the user) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-19...
Page 868 The BSN, BIB, FSN, FIB fields of last transmitted signal unit and result of CRC. Used by CP for automatic FISU transmission. 0x64 LHDR_Tmp Word Temporary storage, used by CP for automatic FISU transmission. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-20 Freescale Semiconductor...
Page 869: Extended Channel Mode Register (Echamr)—Ss7 Mode
The interrupt mask provides bits for enabling/disabling each event defined in the interrupt circular table entry. Other bits provide various channel configuration options. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-21...
Page 870: Extended Channel Mode Register (Echamr)
To prevent a significant number of useless transactions on the external bus, software should always prepare the new BD, or multiple BDs, and set BD[R] before enabling polling. Reserved, must be set. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-22 Freescale Semiconductor...
Page 871: Signal Unit Error Monitor (Suerm)—Ss7 Mode
The Japanese SS7 uses a time interval to monitor errors. If an error is present, it checks every 24 ms. • An error flag is set that indicates whether current frame is errored or not. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-23...
Page 872: Ss7 Configuration Register—Ss7 Mode
SF_DIS Discard short frames (less than 5 octets) 0 Do not discard short frames. 1 Discard short frames. SU_FIL SU Filtering 0 Disable SU filtering. 1 Enable SU filtering. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-24 Freescale Semiconductor...
Page 873: Aerm Implementation
JT Q703 error counter and ensure that an SUERM interrupt is generated on the first SU received in error. After proving period, set the parameters (T and D) to values according to the Japanese SUERM. See section Table 28-12. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-25...
Page 874: Disabling Suerm
Byte 3 Byte 4 Figure 28-11. Mask1 Format Reserved, should be cleared. Byte 5 Figure 28-12. Mask2 Format 28.3.4.4.2 Comparison State Machine The following state machine exists for filtering. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-26 Freescale Semiconductor...
Page 875: Filtering Limitations
To issue this MCC command, refer to Section 14.4, “Command Set.” Use opcode 1110 (0xE). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-27...
Page 876: Octet Counting Mode—Ss7 Mode
RBPTR is user-initialized to RBASE before enabling the channel or after a fatal error before reinitializing the channel. (The address of the BD in use for this channel MCCBASE+8*RTBPTR) The offset relative to dual-port RAM base address + XTRABASE + 8*CH_NUM MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-28 Freescale Semiconductor...
Page 877: Superchannels
SIRAM. Field Channel Number Addr DPRAM_base_address+SCTPBASE+2*MCC_FIFO_number (MCC_FIFO_number is the number written in the MCSEL field of the corresponding SI RAM entry) Figure 28-13. Super Channel Table Entry MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-29...
Page 878: Superchannels And Receiving
1. Superchannel table entries for MCC FIFOs 2, 3 and 4 are programmed such that these FIFOs are managed by the parameters of channel 2. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-30...
Page 879: Transmitter Super Channel Example
Note that the receive examples do not include a superchannel table because a superchannel table is only used on the transmit side. Receive SIRAM entries should always be programmed using the FIFO number MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 880: Receiver Super Channel With Slot Synchronization Example
Thus, slot synchronization is not necessary and the timeslots do not need to be programmed as superchannelled timeslots and the CNT and BYT fields may be programed normally. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-32 Freescale Semiconductor...
Page 881: Mcc Configuration Registers (Mccfx)
00 Group x is used by TDM A. 01 Group x is used by TDM B. 10 Group x is used by TDM C. 11 Group x is used by TDM D. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-33...
Page 882: Mcc Commands
TDM. Not all commands are available in all revisions of silicon and the user should refer to Section 14.4.1.1, “CP Commands,” for further details. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-34 Freescale Semiconductor...
Page 883: Mcc Exceptions
The MCC interrupt reporting scheme has two levels. The circular interrupt tables (illustrated in Figure 28-18) report channel-specific events and are masked by each channel’s INTMSK field located in channel-specific parameter RAM. The MCCE global event register (described in Section 28.8.1, “MCC MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-35...
Page 884: Interrupt Circular Table
Entry”). The user follows this procedure until it reaches an entry with V = 0. It may not be appropriate for an application to process every new entry of all interrupt tables at once, depending on MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-36...
Page 885: Mcc Event Register (Mcce)/Mask Register (Mccm)
This condition occurs if the CP attempts to write a new interrupt entry into an entry that was not handled by the user. Such an entry is identified by V = 1. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-37...
Page 886: Interrupt Circular Table Entry
— Channel Number — Figure 28-20. Interrupt Circular Table Entry SS7 mode only. Otherwise, reserved. Only used in conjunction with AAL1 CES. Table 28-19 describes interrupt circular table fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-38 Freescale Semiconductor...
Page 887 Set whenever a pattern that is not an idle pattern is identified. Idle. Set when the channel’s receiver identifies the first occurrence of idle (0xFFFE) after any non-idle pattern. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-39...
Page 888: Global Transmitter Underrun (Gun)
SIxRam[LST] set and then encounters dead time before the next sync pulse on the line). This may result in anomalous behavior in the SI and therefore an underrun condition. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-40 Freescale Semiconductor...
Page 889: Siram Programming
GUN. The MCC's sensitivity to bandwidth issues is due to the shallowness of the FIFOs and the CPM prioritization of the MCC TX. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 890: Cpm Priority
Issue the INIT RX AND TX command to cover the channels in use. Reprogram the specific MCC channel, global parameters, and any BDs that need to be updated. Enable TDM by setting appropriate bit. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-42 Freescale Semiconductor...
Page 891: Global Overrun (Gov)
Offset + 4 Rx Data Buffer Pointer Offset + 6 Figure 28-21. MCC Receive Buffer Descriptor (RxBD) SS7 mode only. Otherwise, reserved. RxBD fields are described in Table 28-22. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-43...
Page 892 At this point, LG is set (1) and an interrupt may be generated. The length field for this buffer is everything between the opening flag and this last identifying flag. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-44 Freescale Semiconductor...
Page 893: Transmit Buffer Descriptor (Txbd)
This value must be equal to 8*n if CHAMR[TS] = 0 and equal to 8*n - 4 if CHAMR[TS] = 1 (where n is any integer larger than 0). 28.9.2 Transmit Buffer Descriptor (TxBD) Figure 28-22 shows the TxBD. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-45...
Page 894: Mcc Transmit Buffer Descriptor (Txbd)
CP next accesses this BD. However, the R bit is cleared if an error occurs during transmission, regardless of the CM bit setting. — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-46 Freescale Semiconductor...
Page 895: Mcc Initialization And Start/Stop Sequence
1. Program the parallel I/O port interface for the TDM to be used (refer to Chapter 40, “Parallel I/O Ports”). 2. Program the SIU’s interrupt controller to mask or enable MCC-related interrupts as desired (refer Section 4.3.1, “Interrupt Controller Registers”). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 28-47...
Page 896: Stopping And Restarting A Single-Channel
3. Enable the MCC channel(s) as described in Section 28.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode,” Section 28.3.1.4, “Internal Receiver State (RSTATE)—HDLC Mode,” or change the associated SI RAM entry to point to the respective channel. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-48 Freescale Semiconductor...
Page 897: Stopping And Restarting A Superchannel
The user may then estimate how frequently the MCC will need to transfer data on an external bus for a particular channel by calculating how quickly 8 bytes will be sent or received on that channel. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 898 CPM and bus utilization for the MCC channels on a particular TDM, those channels must be dynamically added to the SIRAM programming in an evenly distributed fashion over multiple TDM frames. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 28-50 Freescale Semiconductor...
Page 899: Overview
WANs, LANs, and proprietary networks. FCCs have many physical interface options such as interfacing to TDM buses, ISDN buses, standard modem interfaces, fast Ethernet interface (MII), and MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 29-1...
Page 900 CD) through the appropriate port pins and the interrupt controller. Additional handshake signals can be supported with additional parallel I/O lines. The FCC block diagram is shown in Figure 29-1. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 29-2 Freescale Semiconductor...
Page 901: General Fcc Mode Registers (Gfmrx)
Each FCC contains a general FCC mode register (GFMRx) that defines common FCC options and selects the protocol to be run. The GFMRx are read/write registers cleared at reset. Figure 29-2 shows the GFMR format. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 29-3...
Page 902: General Fcc Mode Register (Gfmr)
• In HDLC and Transparent mode, when TCI=0, data is sent on the falling edge; when TCI=1, on the rising edge. • In Ethernet mode, when TCI=0, data is sent on the rising edge; when TCI=1, on the falling edge. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 29-4 Freescale Semiconductor...
Page 903 This is useful when connecting PowerQUICC IIs in transparent mode since it allows the RTS signal of one PowerQUICC II to be connected directly to the CD signal of another PowerQUICC II. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 904 10 32-bit CCITT CRC (Ethernet and HDLC) (X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1) 11 Reserved MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 29-6 Freescale Semiconductor...
Page 905: Fcc Protocol-Specific Mode Registers (Fpsmrx)
The functionality of the FCC varies according to the protocol selected by GFMR[MODE]. Each FCC has an additional 32-bit, memory-mapped, read/write protocol-specific mode register (FPSMR) that configures them specifically for a chosen mode. The section for each specific protocol describes the FPSMR bits. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 29-7...
Page 906: Fcc Data Synchronization Registers (Fdsrx)
If a new TxBD is added to the BD table while preceding TxBDs have not completed transmission, the new TxBD is processed immediately after the older TxBDs are sent. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 29-8 Freescale Semiconductor...
Page 907: Fcc Buffer Descriptors
All of the transmit BDs for an FCC are grouped into a TxBD circular table with a programmable length. Likewise, receive BDs form an RxBD table. The user can program the start address of the BD tables anywhere in system memory. See Figure 29-5. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 29-9...
Page 908: Fcc Memory Structure
Because BDs are prefetched, the receive BD table must always contain at least one empty BD to avoid a busy error; therefore, RxBD tables must always have at least two BDs. The BDs and data buffers can be anywhere in the system memory. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 29-10 Freescale Semiconductor...
Page 909: Fcc Parameter Ram
Rx parameter RAM can be written only when the receiver is disabled. Note the CLOSE RXBD command does not stop reception, but it does allow the user to extract data from a partially full Rx buffer. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 29-11...
Page 910 Word Tx internal state. The high byte, TSTATE[0–7], contains the function code register; see Section 29.7.1, “FCC Function Code Registers (FCRx).” TSTATE[8–31] is used by the CP and must be cleared initially. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 29-12 Freescale Semiconductor...
Page 911: Fcc Function Code Registers (Fcrx)
TSTATE[0–7] and RSTATE[0–7] in the FCC parameter RAM (see Table 29-4). FCCP Field — Figure 29-7. Function Code Register (FCR x ) FCRx fields are described in Table 29-5. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 29-13...
Page 912: Interrupts From The Fccs
FCCE bit regardless of the corresponding mask bit. To the user it appears as a memory-mapped register that can be read at any time. Bits are cleared by writing ones; writing zeros has MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 29-14...
Page 913: Fcc Mask Registers (Fccmx)
12. Write the SIMR_L to enable interrupts to the CP interrupt controller. 13. Issue an command (with the correct protocol number). INIT TX AND RX PARAMETERS 14. Set GFMR[ENT] and GFMR[ENR]. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 29-15...
Page 914: Fcc Interrupt Handling
2. Remember the TBPTR value taken from the FCC parameter RAM. 3. Issue a “RESTART TX” command using the CPCR. 4. Restore the remembered TBPTR into the FCC parameter RAM. 5. Adjust TxBD handling as described in Section 28.10.1.3. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 29-16 Freescale Semiconductor...
Page 915: Recovery Sequence
I/O line, in which case the CTS signal to the FCC is always asserted. RTS is negated one clock after the last bit in the frame. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 916: Output Delay From Rts Asserted
The negation of CTS forces RTS high and the transmit data to the idle state. If GFMR[CTSS] = 0, the FCC must sample CTS before a CTS lost is recognized. Otherwise, the negation of CTS immediately causes the CTS lost condition. See Figure 29-10. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 29-18 Freescale Semiconductor...
Page 917: Cts Lost
If GFMR[CDS] = 0, CD is sampled on the rising receive clock edge before data is received. If GFMR[CDS] = 1, CD transitions immediately cause data to be gated into the receiver. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 29-19...
Page 918: Disabling The Fccs On-The-Fly
Modifying parameter RAM does not require the FCC to be fully disabled. See the parameter RAM description for when values can be changed. To disable all peripheral controllers, set CPCR[RST] to reset the entire CPM. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 29-20 Freescale Semiconductor...
Page 919: Fcc Transmitter Full Sequence
A shorter sequence is possible if the user prefers to reinitialize the receive parameters to the state they had after reset. This sequence is as follows: 1. Clear GFMR[ENR]. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 29-21...
Page 920: Switching Protocols
Additional changes can be made in the GFMR to change the protocol. 3. Set GFMR[ENT] and GFMR[ENR]. The FCC is enabled with the new protocol. 29.13 Saving Power Clearing an FCC’s ENT and ENR bits minimizes its power consumption. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 29-22 Freescale Semiconductor...
Page 921: Features
The ATM controller has the following features: • Full duplex segmentation and reassembly at 155 Mbps • UTOPIA level II master and slave modes 8/16 bit • AAL5, AAL1, AAL2, AAL0 protocols MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-1...
Page 922 – Sequence number check – Sequence number protection (CRC-3 and parity) check — Segmentation – Segment PDU directly from external memory – Partially filled cells support (configurable on a per-VC basis) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-2 Freescale Semiconductor...
Page 923 — Peak-and-minimum cell rate pacing on a per-VC basis — Up to eight priority levels — Fully managed by CP with no host intervention • Available bit rate (ABR) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-3...
Page 924: Atm Controller Overview
— RxBD table per VC with option of global free buffer pool for AAL5 — TxBD table per VC 30.2 ATM Controller Overview The following sections provide an overview of the transmitter and receiver portions of the ATM controller. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-4 Freescale Semiconductor...
Page 925: Transmitter Overview
(SRTS) generation using external PLL. If this mode is enabled, the PowerQUICC II reads the SRTS code from the external logic and inserts it into four outgoing cells. Section 30.15, “SRTS Generation and Clock Recovery Using External Logic.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-5...
Page 926: Aal1 Ces Transmitter Overview
The receiver ATM cell size is 53–65 bytes. The cell includes: 4 bytes ATM cell header, 1 byte HEC, which can be checked by setting FPSMR[HECC] (refer to Table 30-47), and 48 bytes payload. User-defined cells MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-6 Freescale Semiconductor...
Page 927: Aal5 Receiver Overview
ATM receiver closes the current RxBD, sets RxBD[SNE], and returns to the hunt state. The receiver then waits for a cell with a valid structured pointer to regain synchronization. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-7...
Page 928: Aal1 Ces Receiver Overview
(VBR-NRT, ABR, UBR) are scheduled at low-priority levels. Up to eight priority levels are available. 30.3.1 APC Modes and ATM Service Types The ATM Forum (http://www.atmforum.com) defines the service types described in Table 30-1. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-8 Freescale Semiconductor...
Page 929: Apc Unit Scheduling Mechanism
The PCR parameter in the TCT, or the SCR or MCR parameters in the TCT extension (TCTE) determine the channel’s actual rate. Number of Slots Current Slot Cell Rescheduling Figure 30-1. APC Scheduling Table Mechanism MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-9...
Page 930: Determining The Scheduling Table Size
(PCR = peak cell rate, PCRF = peak cell rate fraction, NOS = number of slots): PCR = 1 and PCRF = 0 PCR = NOS - 1 and PCRF = 0 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-10 Freescale Semiconductor...
Page 931: Determining The Time-Slot Scheduling Rate Of A Channel
PCR_FRACTION is in units of 1/256 slots, the fraction must be converted as follows: 1.241 = 1+0.241 × 256/256 =1+ 61.79/256 ~ 1 + 62/256 PCR = 1 PCR_FRACTION = 62 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-11...
Page 932: Peak And Sustain Traffic Type (Vbr)
SCR [slots] = (155.52 Mbps)/(2 Mbps × 8) = 9.72 9.72 = 9 + (0.72 × 256/256) = 9 + 184.32/256 ~ 9 + 185/256 SCR = 9 SCR_FRACTION = 185 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-12 Freescale Semiconductor...
Page 933: Handling The Cell Loss Priority (Clp)—Vbr Type 1 And 2
The PowerQUICC II supports two ways to look up addresses for incoming cells: • External CAM lookup • Address compression Writing to GMODE[ALM] (address-lookup-mechanism bit) in the parameter RAM selects the mechanism. Both mechanisms are described in the following sections. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-13...
Page 934: External Cam Lookup
The GFC, VPI, and VCI of the current channel. Ch Code Pointer to internal or external connection table. — Reserved, should be cleared. Match status. 0 Match was found. 1 Match was not found. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-14 Freescale Semiconductor...
Page 935: Address Compression
16-bit mask (VC_MASK) and the VC-level table offset (VCOFFSET) for the next level of address mapping. The VC_MASK selects VCI bits 4–10, which is used with VCT_BASE and VCOFFSET MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 936: Vp-Level Address Compression Table (Vplt)
Table 30-4. VCOFFSET Calculation Examples for Contiguous VCLTs VP-Level Number of Ones VC-Level VC_MASK VCOFFSET Table Entry in VC_MASK Table Size 0x0237 = 64 entries 0x0230 = 8 entries MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-16 Freescale Semiconductor...
Page 937: Vc-Level Address Compression Tables (Vclts)
If they are not, the cell is considered a misinserted cell. An example of VC-level table entry address calculation is shown in Table 30-6. Note that VCOFFSET is assumed to be 0x100 for this example. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-17...
Page 938: Misinserted Cells
VCI value: 3, 4, 6, 7–15. To enable VCI filtering set the associated bit in the VCIF entry in the parameter RAM. Figure 30-9 shows a flowchart of the ATM cell flow. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-18 Freescale Semiconductor...
Page 939: Available Bit Rate (Abr) Flow Control
The source sends forward RM cells specifying its chosen transmit rate (source ER). A congested switch along the network may decrease ER to the exact rate it can MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 940: The Abr Model
6. When B-RM is received with CI=0 and NI=0 (no increase), ACR is increased by RIF × PCR (rate increase factor). The new ACR is determined first by letting ACRtemp be the min of (ACR, ER), and then taking the max of (ACRtemp, MCR). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-20 Freescale Semiconductor...
Page 941: Abr Flow Control Destination End-System Behavior
RM cell overwrites the old RM cell. 30.5.1.3 ABR Flowcharts The PowerQUICC II’s ABR transmit and receive flow control is described in the following flowcharts. Figure 30-11, Figure 30-12, Figure 30-13, and Figure 30-14. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-21...
Page 942: Abr Transmit Flow
Send RM (DIR = forward, CCR = ACR, ER = PCR, CI = NI = 0, CLP =1) Schedule: Time_to_send = now+1/TCR EXIT ACR>=TCR RM/DATA In Rate Cell Tx Figure 30-11. ABR Transmit Flow MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-22 Freescale Semiconductor...
Page 943: Abr Transmit Flow (Continued)
First-turn = TRUE First-turn = Flag indicates first turn of RM cell Unack = Unack+1 with priority over data cells. Count = Count+1 EXIT Figure 30-12. ABR Transmit Flow (Continued) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-23...
Page 944: Abr Transmit Flow (Continued)
Turn-around = first-turn = FALSE Count = Count+1 EXIT Data Cell Tx Send Data Cell CLP = EFCI = 0 Count = Count+1 Schedule:Time_to_send = Now+1/ACR EXIT Figure 30-13. ABR Transmit Flow (Continued) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-24 Freescale Semiconductor...
Page 945: Rm Cell Structure
RM cell supported by the PowerQUICC II. For more information, see the ABR flow-control traffic management specification (TM 4.0) on the ATM Forum website. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-25...
Page 946: Rm Cell Rate Representation
Figure 30-16. Rate Formula for RM Cells Initialize the traffic parameters (ER, MCR, PCR, or ICR) in the ABR protocol-specific connection tables using the rate formula in Figure 30-16. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-26 Freescale Semiconductor...
Page 947: Abr Flow Control Setup
End-to-end OAM F5 flow cell xxxx aaaa_aaaa aaaa_aaaa_aaaa_aaaa a = available for use by the appropriate ATM layer function Table 30-9 lists pre-assigned header values at the network-node interface (NNI). MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-27...
Page 948: Virtual Channel (F5) Flow Mechanism
TCT to operate in AAL0 mode. Enable the CR10 (CRC-10 insertion) mode as described in Section 30.10.2.3.3, “AAL0 Protocol-Specific TCT.” Prepare the OAM F4/F5 flow cell and MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-28 Freescale Semiconductor...
Page 949: Performance Monitoring
FMCs only. TRCC , BLER, and TRCC appear in BRCs only. Figure 30-17. Performance Monitoring Cell Structure (FMCs and BRCs) Table 30-10 describes performance monitoring cell fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-29...
Page 950: Running A Performance Block Test
, BLER) and transfers the cell to the receive raw cell queue. The user can monitor the BRC cell results and transfer the cell to the transmit raw cell queue. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-30 Freescale Semiconductor...
Page 951: Pm Block Generation
BRC Cell BRC Cell BRC Cell TUC0 TUC0 TUC0 TUC0+1 TUC0+1 TUC0+1 TRCC0 TRCC0 TRCC0 TRCC0+1 TRCC0+1 TRCC0+1 BLER BLER BLER TSTP TSTP TSTP Figure 30-18. FMC, BRC Insertion MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-31...
Page 952: Brc Performance Calculations
RAM determines the offset from the beginning of the UDC extra header to the UEAD entry. The offset should be half-word aligned (even address). See Section 30.10.1, “Parameter RAM.” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-32 Freescale Semiconductor...
Page 953: Atm Layer Statistics
Automatic Data Forwarding The basic concept of automatic data forwarding is to program the ATM controller and the MCC to process the same BD table, as shown in Figure 30-21. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-33...
Page 954: Using Interrupts In Automatic Data Forwarding
RxBD is closed, RxBD[E] is set (because it is operating in opposite E-bit polarity), and the core is interrupted. The core then starts the MCC transmitter. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-34...
Page 955: Timing Issues
The core can keep the CAS block in memory and connect to the framer only when the CAS changes. The core can use regular read and write cycles when connecting to the framer through a parallel interface. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-35...
Page 956: Trunk Condition
Hword Tx cell temporary base address. Points to total of 64 bytes reserved dual-port RAM area used by the CP. Should be 64-byte aligned. User-defined offset from dual-port RAM base. (Recommended address space: 0x3000–0x4000 or 0xB000–0xC000) MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-36 Freescale Semiconductor...
Page 957 BD_BASE_EXT[8–31] should be zero. User-defined. 0x70 VPT_BASE / Word Base address of the address compression VP table/external CAM. EXT_CAM_BASE User-defined. 0x74 VCT_BASE Word Base address of the address compression VC table. User-defined. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-37...
Page 958 Hword (ABR only) Controls the maximum cells the source may send for each F-RM cell. Set to 32 cells. 0xAE Hword (ABR only) Controls the bandwidth between F-RM, B-RM and user data cell. Set to 2 cells. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-38 Freescale Semiconductor...
Page 959: Determining Uead_Offset (Uead Mode Only)
VC x VCI filtering enable 7–15 0 Do not send cells with this VCI to the raw cell queue. 1 Send cells with this VCI to the raw cell queue. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-39...
Page 960: Global Mode Entry (Gmode)
0 Do not check unallocated bits during address compression. 1 Check unallocated bits during address compression. EVPT External address compression VP table 0 VP table resides in dual-port RAM. 1 VP table reside in external memory. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-40 Freescale Semiconductor...
Page 961: Connection Tables (Rct, Tct, And Tcte)
255 indicate external channels. Channel code one is reserved as the raw cell queue and cannot be used for another purpose. The channel code is used to specify MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 962: Receive Connection Table (Rct)
(The transmit connection table base address parameters are INT_TCT_BASE, EXT_TCT_BASE, INT_TCTE_BASE, and EXT_TCTE_BASE.) 30.10.2.2 Receive Connection Table (RCT) Figure 30-25 shows the format of an RCT entry. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-42 Freescale Semiconductor...
Page 963: Receive Connection Table (Rct) Entry
Offset + 0x18 Offset + 0x1A MRBLR Offset + 0x1C — RBD_BASE Offset + 0x1E RBD_BASE — Figure 30-25. Receive Connection Table (RCT) Entry Table 30-16 describes RCT fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-43...
Page 964 0 Do not send cells with PTI=101 to the raw cell queue. 1 Send cells with PTI=101 to the raw cell queue. 12–13 — Reserved, should be cleared. 14–15 INTQ Points to one of four interrupt queues available. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-44 Freescale Semiconductor...
Page 965: Aal5 Protocol-Specific Rct
PMT field is updated. 30.10.2.2.1 AAL5 Protocol-Specific RCT Figure 30-26 shows the AAL5 protocol-specific area of an RCT entry. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-45...
Page 966: Aal5-Abr Protocol-Specific Rct
Buffer pool. Global buffer allocation mode only. Points to one of four free buffer pools. Section 30.10.5.2.4, “Free Buffer Pool Parameter Tables.” 30.10.2.2.2 AAL5-ABR Protocol-Specific RCT Figure 30-27 shows the AAL5-ABR protocol-specific area of an RCT entry. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-46 Freescale Semiconductor...
Page 967: Aal1 Protocol-Specific Rct
Structured Pointer (SP) Offset + 0x14 RBDCNT Offset + 0x16 — Offset + 0x18 — SNEM — RXBM — Figure 30-28. AAL1 Protocol-Specific RCT Table 30-19 describes AAL1 protocol-specific RCT fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-47...
Page 968 RxBD count. Indicates how may bytes remain in the current Rx buffer. Initialized with MRBLR whenever the CP opens a new buffer. 0x16 0–12 — Reserved, should be cleared. 13–15 Sequence number. Used by the CP to check incoming cell’s sequence number. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-48 Freescale Semiconductor...
Page 969: Aal0 Protocol-Specific Rct
0 RxBD[E] is interpreted normally (1 = empty, 0 = not empty). 1 RxBD[E] is handled in negative logic (0 = empty, 1 = not empty). 11-15 — Reserved, should be cleared. 0x10 — — Reserved, should be cleared. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-49...
Page 970: Aal1 Ces Protocol-Specific Rct
APC Linked Channel (APCLC) Offset + 0x18 ATM Cell Header (VPI,VCI,PTI,CLP) Offset + 0x1a Offset + 0x1C — TBD_BASE Offset + 0x1E TBD_BASE STPT IMK Figure 30-30. Transmit Connection Table (TCT) Entry MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-50 Freescale Semiconductor...
Page 971 ATM Controller and AAL0, AAL1, and AAL5 Table 30-21 describes general TCT fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-51...
Page 972 ATM Controller and AAL0, AAL1, and AAL5 MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-52 Freescale Semiconductor...
Page 973 APC scheduling table. The host can issue another command only after the CP clears VCON. ATM TRANSMIT 14–15 INTQ Points to one of four interrupt queues available. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-53...
Page 974 APC linked channel. Used by the CP. Initialize to 0 (null pointer). 0x18 — ATMCH ATM cell header. Holds the full (4-byte) ATM cell header of the current channel. The transmitter appends ATMCH to the cell payload during transmission. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-54 Freescale Semiconductor...
Page 975: Aal5 Protocol-Specific Tct
Description 0x10 Tx CRC CRC32 temporary result. 0x14 Total Message Length This field is used by the CP. 30.10.2.3.2 AAL1 Protocol-Specific TCT Figure 30-32 shows the AAL1 protocol-specific TCT. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-55...
Page 976: Aal1 Protocol-Specific Tct
SRTS_TMP, and then inserts SRTS_TMP into the next four cells with an odd 4–15 Structured pointer. Used by the CP to calculate the structured pointer. Should be cleared initially. Structured format only. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-56 Freescale Semiconductor...
Page 977: Aal0 Protocol-Specific Tct
Refer to Section 31.9.2.1, “AAL1 CES Protocol-Specific TCT.” 30.10.2.3.5 AAL2 Protocol-Specific TCT Refer to Section 32.3.5.1, “AAL2 Protocol-Specific TCT.” 30.10.2.3.6 VBR Protocol-Specific TCTE Figure 30-34 shows the VBR protocol-specific TCTE. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-57...
Page 978: Ubr+ Protocol-Specific Tcte
CLP=1 cells are rescheduled by PCR. 1–15 — Reserved, should be cleared. 0x0E– — — Reserved, should be cleared. 0x1E 30.10.2.3.7 UBR+ Protocol-Specific TCTE Figure 30-35 shows the UBR+ protocol-specific TCTE. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-58 Freescale Semiconductor...
Page 979: Abr Protocol-Specific Tcte
APC reduces the scheduling rate from PCR to MCR. 0x06– — — Reserved, should be cleared. 0x1E 30.10.2.3.8 ABR Protocol-Specific TCTE Figure 30-36 shows the ABR protocol-specific TCTE. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-59...
Page 980: Abr Protocol-Specific Tcte
Congestion indication–turn-around cell. Holds the CI of the last received F-RM cell. If another F-RM cell arrives before the previous F-RM cell was turned around, CI-TA is overwritten by the new RM cell’s CI. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-60 Freescale Semiconductor...
Page 981 The ADTF value is defined by the system clock and the time stamp timer prescaler; see Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR).” For a time stamp prescaler of 1 µs, ADTF should be programmed to 500m/(1µs × 1024)= 488. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-61...
Page 982: Oam Performance Monitoring Tables
Offset + 0x16 Offset + 0x18 — Offset + 0x1A Offset + 0x1C Offset + 0x1E Figure 30-37. OAM Performance Monitoring Table Table 30-28 describes fields in the performance monitoring table. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-62 Freescale Semiconductor...
Page 983: Apc Data Structure
30.10.4 APC Data Structure The APC data structure consists of three elements: the APC parameter tables for the PHY devices, the APC priority table, and the APC scheduling tables. See Figure 30-38. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-63...
Page 984: Apc Parameter Tables
Byte Max iteration allowed. Number of scan iterations allowed in the APC. User-defined. This parameter limits the time spent in a single APC routine, thereby avoiding excessive APC latency. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-64 Freescale Semiconductor...
Page 985: Apc Priority Table
1 slot N Slot Half Word Entry APC_LEVi_END Figure 30-39. The APC Scheduling Table Structure Slot N+1 is used as a control slot, as shown in Figure 30-40. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-65...
Page 986: Atm Controller Buffer Descriptors (Bds)
CP removes the channel from the APC and clears TCT[VCON]. The core must issue a new command to restart transmission. TRANSMIT Figure 30-41 shows the ready bit in the TxBD tables and their associated buffers for two example ATM channels. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-66 Freescale Semiconductor...
Page 987: Receive Buffer Operation
Figure 30-42 shows the empty bit in the RxBD tables and their associated buffers for two example ATM channels. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-67...
Page 988: Global Buffer Allocation
ATM channels’ BD tables and one free buffer pool. Both channels are associated with free buffer pool 1. The CP allocates the first two buffers of buffer pool 1 to channel 1 and the third to channel 4. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-68 Freescale Semiconductor...
Page 989: Free Buffer Pools
W = 0 Buffer Pointer V = 1 W = 1 Buffer Pointer Figure 30-44. Free Buffer Pool Structure Figure 30-45 describes the structure of a free buffer pool entry. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-69...
Page 990: Free Buffer Pool Parameter Tables
Free buffer pool pointer. Pointer to the current entry in the free buffer pool. Initialize to FBP_BASE. 0x08 — FBP_ENTRY_EXT Free buffer pool entry extension. FBP_ENTRY_EXT[0–3] holds the four left bits of FBP_ENTRY. FBP_ENTRY_EXT[4–15] should be cleared. User-defined. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-70 Freescale Semiconductor...
Page 991: Atm Controller Buffers
— — CLP CNG ABRT CPUU LNE CRE Offset + 0x02 Data Length (DL) Offset + 0x04 Rx Data Buffer Pointer (RXDBPTR) Offset + 0x06 Figure 30-46. AAL5 RxBD MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-71...
Page 992 47 or less than zero octets. Rx CRC error. Indicates CRC32 error in the current AAL5 PDU. Set only for the last BD of the frame. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-72 Freescale Semiconductor...
Page 993: Aal1 Rxbd
Offset + 0x00 — — — Offset + 0x02 Data Length Offset + 0x04 Rx Data Buffer Pointer Offset + 0x06 Figure 30-47. AAL1 RxBD Table 30-36 describes AAL1 RxBD fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-73...
Page 994: Aal0 Rxbd
Offset + 0x02 Data Length (DL)/Channel Code (CC) Offset + 0x04 Rx Data Buffer Pointer (RXDBPTR) Offset + 0x06 Figure 30-48. AAL0 RxBD Table 30-37 describes AAL0 RxBD fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-74 Freescale Semiconductor...
Page 995: Aal1 Ces Rxbd
This pointer must be burst-aligned. 30.10.5.7 AAL1 CES RxBD Refer to Section 31.12.1, “AAL1 CES RxBD.” 30.10.5.8 AAL2 RxBD Refer to Section 32.4.4.4, “CPS Receive Buffer Descriptor (RxBD).” MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-75...
Page 996: Aal5, Aal1 Ces User-Defined Cell—Rxbd Extension
CLP CNG — Offset + 0x02 Data Length (DL) Offset + 0x04 Tx Data Buffer Pointer (TXDBPTR) Offset + 0x06 Figure 30-50. AAL5 TxBD Table 30-38 describes AAL5 TxBD fields. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-76 Freescale Semiconductor...
Page 997: Aal1 Txbds
8-byte-aligned. The buffer may reside in either internal or external memory. This value is not modified by the CP. 30.10.5.11 AAL1 TxBDs Figure 30-51 shows the AAL1 TxBD. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-77...
Page 998: Aal0 Txbds
Figure 30-52 shows AAL0 TxBDs. Note that the data length field is calculated internally as 52 bytes, plus the extra header length (defined in FPSMR[TEHS]) when in UDC mode. MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-78 Freescale Semiconductor...
Page 999: Aal1 Ces Txbds
8-byte-aligned. The buffer may reside in either internal or external memory. This value is not modified by the CP. 30.10.5.13 AAL1 CES TxBDs Refer to Section 31.12.2, “AAL1 CES TxBDs MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 Freescale Semiconductor 30-79...
Page 1000: Aal2 Txbds
0x0006 Offset + 0x16 0x0001 Offset + 0x18 0x0005 Offset + 0x1A 0x0002 Offset + 0x1C 0x0008 Offset + 0x1E 0x000F Figure 30-54. AAL1 Sequence Number (SN) Protection Table MPC8260 PowerQUICC II Family Reference Manual, Rev. 2 30-80 Freescale Semiconductor...

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Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual

Table of Contents

Chapter 3 System Interface Unit (SIU)

Chapter 1 Communications Processor Module (CPM)

Chapter 2 G2 Processor Core Features

Chapter 5

Chapter 6

Chapter 7 Address Bus Arbitration Signals

Chapter 8

Chapter 9

Chapter 10

Chapter 11 Memory Controller

Chapter 12

Chapter 13 Powerquicc II Restrictions

Chapter 14 Communications Processor Module

Chapter 15

Chapter 16

Chapter 17

Chapter 18

Chapter 19

Chapter 20 The General SCC Mode Registers (GSMR1–GSMR4)

Chapter 21

Chapter 22

Chapter 23

Chapter 24

Chapter 25

Chapter 26 SCC Appletalk Mode

Chapter 27 Common SMC Settings and Configurations

Chapter 28 MCC Data Structure Organization

Chapter 29

Chapter 30

Chapter 32

Chapter 31

Chapter 33

Chapter 34 Receive ATM 2-Cell FIFO

Chapter 35

Chapter 36

Chapter 37

Chapter 38

Chapter 40 Port Registers

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Summary of Contents for Freescale Semiconductor MPC8260 PowerQUICC II