Freescale Semiconductor MCF54455 Reference Manual page 509

SDRAM Controller (SDRAMC)
Table 21-13. Mobile DDR Extended-Mode Register Field Descriptions
Field
BA1–BA0 Bank address. These must be set to 10 to select the extended mode register.
A11–A7 Reserved, must be cleared.
A6–A5 Drive strength.
DS 00 Full strength
01 Half strength
10 Quarter strength
11 One-eighth strength
A4–A3 Temperature-compensated self-refresh. Check the SDRAM manufacturer's spec because the use of the TCSR
TCSR settings can vary from memory to memory.
A2–A0 Partial array self refresh coverage.
PASR 000 Full array
001 Half array
010 Quarter array
101 One-eighth array
110 One-sixteenth array
All other settings are reserved.
21.5.1.6.4 DDR2 Mode Register Definition
Figure 21-12 shows the mode register used by DDR2 SDRAMs. This is the SDRAM's extended mode
register, and not the SDRAMC's mode/extended mode register (SDMR) described in
"SDRAM Mode/Extended Mode Register
BA1 BA0
Field 0 0
Field
BA1–BA0 Bank address. These must be zero to select the mode register
A12 Active Power Down exit time.
PD 0 Use Fast exit (Use t
1 Use Slow exit (Use t
A11–A9 Write recovery for precharge. The t
WR clock cycles is calculated by dividing t
(WR[cycles] = t
with t to determine t
RP
000 Reserved
001 2
010 3
011 4
100 5
101 6
11x Reserved
21-22
(SDMR)".
A12 A11 A10 A9
PD WR DLL
Figure 21-12. DDR2 Mode Register
Table 21-14. DDR2 Mode Register Field Descriptions
)
XARD
)
XARDS
max determines WR
CK
WR
(ns)/t (ns)). The mode register must be programmed to this value. This is also used
WR CK
.
DAL
Description
A8 A7 A6 A5
TM CL
Description
and t
min CK
(in ns) by t (in ns) and rounding up to the next integer
CK
Section 21.4.1,
A4 A3 A2 A1
BT BL
min determines WR . WR in
max
Freescale Semiconductor
A0