Debugging In A Virtual Environment; Virtual Memory Architecture Processor Support - Freescale Semiconductor MCF54455 Reference Manual

4.3.1.2.11 Supervisor Protection
Each instruction or data reference is a supervisor or user access. The CPU's status register supervisor bit
(SR[S]) determines the operating mode. New ACR and CACR bits protect supervisor space. See
Table 4-10.
4.3.2

Debugging in a Virtual Environment

To support debugging in a virtual environment, numerous enhancements are implemented in the ColdFire
debug architecture. These enhancements are collectively called debug revision D and primarily relate to
the addition of an 8-bit address space identifier (ASID) to yield a 40-bit virtual address. This expansion
affects two major debug functions:
• The ASID is optionally included in the hardware breakpoint registers specification. For example,
the four PC breakpoint registers are expanded by 8 bits each, so that a specific ASID value can be
part of the breakpoint instruction address. Likewise, data address/data breakpoint registers are
expanded to include an ASID value. The new control registers define if and how the ASID is
included in the breakpoint comparison trigger logic.
• The debug module implements the concept of ownership trace in which an ASID value can be
optionally displayed as part of real-time trace. When enabled, real-time trace displays instruction
addresses on any change-of-flow instruction that is not absolute or PC-relative. For debug
revision D architecture, the address display is expanded to include ASID contents optionally, thus
providing the complete instruction virtual address on these instructions. Additionally, when a
_ serial BDM command is loaded from the external development system, the processor
SYNC PC
displays the complete virtual-instruction address, including the 8-bit ASID value.
The MMU control registers are accessible through serial BDM commands. See
Module."
4.3.3

Virtual Memory Architecture Processor Support

To support the MMU, enhancements have been made to the exception model, the stack pointers, and the
access error stack frame.
4.3.3.1 Precise Faults
To support demand-paging, all memory references require precise, recoverable faults. The ColdFire
instruction-restart mechanism ensures a faulted instruction restarts from the beginning of execution; in
other words, no internal state information is saved when an exception occurs and none is restored when
the handler ends. Given the PC address defined in the exception stack frame, the processor reestablishes
program execution by transferring control to the given location as part of the RTE (return from exception)
instruction.
For a detailed description, see
Freescale Semiconductor
Section 3.3.4.16, "Precise Faults."
Memory Management Unit (MMU)
Chapter 34, "Debug
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