Introduction - Freescale Semiconductor MCF54455 Reference Manual

Chapter 12
Serial Boot Facility (SBF)
12.1

Introduction

It is nearly impossible to dedicate and very impractical to share pins for the numerous available power-up
options on today's complex, highly-integrated processors. The serial boot facility (SBF), shown in
Figure 12-1, solves this problem by providing the user with the capability to store and load all device reset
configuration data and user code from an external SPI memory. This method requires only a minimal
number of I/O pins.
On-chip
Modules
Reset
Controller
Chip
Configuration
Module
Processor
Memory
12.1.1 Overview
The SBF interfaces to an external SPI memory to read configuration data and boot code during the
processor reset sequence if BOOTMOD[1:0] equals 11. By reading data stored in the SPI memory, the SBF
adjusts the SPI memory clock frequency, configures an extended set of power-up options for the processor,
and optionally loads code into the on-chip SRAM. Through interaction with the reset controller, the SBF
performs these actions so that the chip is properly configured after exiting the reset state.
Freescale Semiconductor
SBF
Clock
Control
Control
Registers
RAM
Interface
Figure 12-1. SBF Block Diagram
SBF_CK
SBF_CS
Read
Command
SBF_DO
SBF_DI
Deserializer/
Debounce
12-1