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Memory Management Unit (MMU)
4.3.3.2
Supervisor/User Stack Pointers
To provide the required isolation among these operating modes as dictated by a virtual memory
management scheme, a user stack pointer (A7–USP) is added. The appropriate stack pointer register (SSP,
USP) is accessed as a function of the processor's operating mode.
In addition, the following two privileged M68000 family instructions to load/store the USP are added to
the ColdFire instruction set architecture:
move.l
Ay,USP
move.l
USP,Ax
The address register number is encoded in the three low-order bits of the opcode.
These instructions are described in detail in
4.3.3.3
Access Error Stack Frame Additions
ColdFire exceptions generate a standard 2-longword stack frame, signaling the contents of the SR and PC
at the time of the exception, the exception type, and a 4-bit fault status field (FS). The first longword
contains the 16-bit format/vector word (F/V) and the 16-bit status register. The second contains the 32-bit
program counter address of the faulted instruction. For more information, see
Stack Frame Definition."
31 30 29 28 27
SSP
Format
FS[3:2]
+ 0x4
The FS field is used for access and address errors. To optimize TLB miss-exception handling, new FS
encodings (as shown in
Table
FS[3:0]
0000
0001 – 0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
4-16
# move to USP: opcode = 0x4E6{0-7}
# move from USP: opcode = 0x4E6{8–F}
Section 4.3.9, "MMU
26 25 24 23 22 21 20 19 18 17
Vector
Program Counter
Figure 4-10. Exception Stack Frame Form
4-11) allow quick error classification.
Table 4-11. Fault Status Encodings
Not an access or address error
Error (for example, protection fault) on instruction fetch
TLB miss on opword of instruction fetch (New for MMU)
TLB miss on extension word of instruction fetch (New for MMU)
IFP access error while executing in emulator mode (New for MMU)
Attempted write of protected space
TLB miss on data write (New for MMU)
Instructions."
16 15 14 13 12 11 10 9
FS[1:0]
Status Register
Definition
Reserved
Error on data write
Reserved
Error on data read
Section 3.3.3.1, "Exception
8
7
6
5
4
3
2
1
0
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