Endianness - Freescale Semiconductor MCF54455 Reference Manual

Advanced Technology Attachment (ATA)
Address
0x9000_0016 TIME_SS—t
0x9000_0017 TIME_CYC—t
0x9000_0018 FIFO_DATA32—32-bit wide data port to/from FIFO
0x9000_001C FIFO_DATA16—16-bit wide data port to/from FIFO
0x9000_0020 FIFO_FILL—FIFO filling in halfwords
0x9000_0024 ATA_CR—ATA interface control register
0x9000_0028 ATA_ISR—Interrupt status register
0x9000_002C ATA_IER—Interrupt enable register
0x9000_0030 ATA_ICR—Interrupt clear register
0x9000_0034 FIFO_ALARM—FIFO alarm threshold
0x9000_00A0 DRIVE_DATA—Drive data register
0x9000_00A4 DRIVE_FEATURES—Drive features register
0x9000_00A8 DRIVE_SECTOR_COUNT—Drive sector count register
0x9000_00AC DRIVE_LBA_LOW—Drive LBA low register
0x9000_00B0 DRIVE_LBA_MID—Drive LBA middle register
0x9000_00B4 DRIVE_LBA_HIGH—Drive LBA high register
0x9000_00B8 DRIVE_DEV_HEAD—Drive device head register
0x9000_00BC DRIVE_STATUS—Drive status register
DRIVE_COMMAND—Drive command register
0x9000_00D8 DRIVE_ALT_STATUS—Drive alternate status register
DRIVE_CONTROL—Drive control register
1
See the AT Attachment - 6 with Packet Interface specification available at http://www.t13.org.
23.3.1

Endianness

The ATA interface works in big endian mode.The few 16-bit and 32-bit registers represent strings of 2 or
4 bytes. The byte order in the 16-bit or 32-bit register is as follows:
• Big endian, 32-bit register
— bits [31:24]: byte 0
— bits [23:16]: byte 1
23-6
Table 23-2. ATA Memory Map (continued)
Register
UDMA timing register
ss
and t UDMA timing register
cyc 2cyc
FIFO Registers
ATA Interface Registers
Drive Registers
Width Access Reset Value
8 R/W 0x01
8 R/W 0x01
32 R/W Undefined
16 R/W Undefined
8 R 0x00
8 R/W 0x00
8 R See Section
8 R/W See Section
8 W Undefined
8 R/W 0x00
1
16 R/W See Spec
1
8 R/W See Spec
1
8 R/W See Spec
1
8 R/W See Spec
1
8 R/W See Spec
1
8 R/W See Spec
1
8 R/W See Spec
1
8 R See Spec
1
8 W See Spec
1
8 R See Spec
1
8 W See Spec
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