Freescale Semiconductor MCF54455 Reference Manual page 706

first enabled time slot and subsequently, data is loaded from FIFO 1 and FIFO 0 alternately and
transmitted. Similarly, the first received data is sent to FIFO 0 and subsequent data is sent to FIFO 1 and
FIFO 0 alternately. Time slots are selected through the transmit and receive time slot mask registers
(SSI_TMASK and SSI_RMASK).
27.4.1.2.1 Network Mode Transmit
The transmit portion of SSI is enabled when the SSI_CR[SSI_EN and TE] bits are set. However, for
continuous clock when the TE bit is set, the transmitter is enabled only after detection of a new frame sync
(transmission starts from the next frame boundary).
Normal start-up sequence for transmission:
• Write the data to be transmitted to the SSI_TX register. This clears the TDE flag.
• Set the SSI_CR[TE] bit to enable the transmitter on the next word boundary (for continuous clock).
• Enable transmit interrupts.
Alternately, the user may decide not to transmit in a time slot by writing to the SSI_TMASK. The TDE
flag is not cleared, but the SSI_TXD port remains disabled during the time slot. When the frame sync is
detected or generated (continuous clock), the first enabled data word is transferred from the SSI_TX
register to the TXSR and is shifted out (transmitted). When the SSI_TX register is empty, the TDE bit is
set, which causes a transmitter interrupt (if the FIFO is disabled) to be sent if the TIE bit is set. Software
can poll the TDE bit or use interrupts to reload the SSI_TX register with new data for the next time slot.
Failing to reload the SSI_TX register before the TXSR is finished shifting (empty) causes a transmitter
underrun error (the TUE bit is set). If the FIFO is enabled, the TFE flag is set in accordance with the
watermark setting and this flag causes a transmitter interrupt to occur.
Clearing the TE bit disables the transmitter after completion of transmission of the current frame. Setting
the TE bit enables transmission from the next frame. During that time the SSI_TXD port is disabled. The
TE bit should be cleared after the TDE bit is set to ensure that all pending data is transmitted.
To summarize, the network mode transmitter generates interrupts every enabled time slot and requires the
processor to respond to each enabled time slot. These responses may be:
• Write data in data register to enable transmission in the next time slot.
• Configure the time slot register to disable transmission in the next time slot (unless the time slot is
already masked by the SSI_TMASK register bit).
• Do nothing—transmit underrun occurs at the beginning of the next time slot and the previous data
is re-transmitted.
In two channel operation, both channels (data registers, FIFOs, interrupts, and DMA requests) operate in
the same manner, as described above. The only difference is interrupts related to the second channel are
generated only if this mode of operation is selected (TDE1 is low by default).
27.4.1.2.2 Network Mode Receive
The receiver portion of the SSI is enabled when both the SSI_CR[SSI_EN and RE] bits are set. However,
the receive enable only takes place during that time slot if RE is enabled before the second to last bit of the
word. If the RE bit is cleared, the receiver is disabled at the end of the current frame. The SSI module is
Freescale Semiconductor
Synchronous Serial Interface (SSI)
27-39