Microcontroller Initialization - Freescale Semiconductor MCF54455 Reference Manual

Fast Ethernet Controllers (FEC0 and FEC1)
Table 26-32 defines Ethernet MAC registers requiring initialization.
Table 26-33 defines FEC FIFO/DMA registers that require initialization.
Table 26-33. FEC User Initialization (Before ECR[ETHER_EN])
26.5.4

Microcontroller Initialization

In the FEC, the descriptor control RISC initializes some registers after ECRn[ETHER_EN] is asserted.
After the microcontroller initialization sequence is complete, hardware is ready for operation.
Table 26-34 shows microcontroller initialization operations.
26-35
Table 26-32. User Initialization (Before ECRn[ETHER_EN])
Description
Initialize EIMRn
Clear EIRn (write 0xFFFF_FFFF)
TFWRn (optional)
IALRn / IAURn
GAURn / GALRn
PALRn / PAURn (only needed for full duplex flow control)
OPDn (only needed for full duplex flow control)
MSCRn (optional)
Clear MIB_RAMn
Description
Initialize FRSRn (optional)
Initialize EMRBRn
Initialize ERDSRn
Initialize ETDSRn
Initialize (Empty) Transmit Descriptor ring
Initialize (Empty) Receive Descriptor ring
Table 26-34. Microcontroller Initialization
Description
Initialize BackOff Random Number Seed
Activate Receiver
Activate Transmitter
Clear Transmit FIFO
Clear Receive FIFO
RCRn
TCRn
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