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ColdFire Core
BDM: 0x801 (VBR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3.2.9
Status Register (SR)
The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control
bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits (CCR) are
accessible. The control bits indicate the following states for the processor: trace mode (T bit), supervisor
or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access
when in supervisor mode.
The lower byte of the SR (the CCR) must be loaded explicitly after reset and
before any compare (CMP), Bcc, or Scc instructions execute.
BDM: 0x80E (SR)
15
14
13
R
0
T
S
W
Reset
0
0
1
Field
15
Trace enable. When set, the processor performs a trace exception after every instruction.
T
14
Reserved, must be cleared.
13
Supervisor/user state.
S
0 User mode
1 Supervisor mode
12
Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or
M
move to SR instructions.
11
Reserved, must be cleared.
3-11
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Base Address
Figure 3-7. Vector Base Register (VBR)
System Byte
12
11
10
9
0
M
I
0
0
1
1
Figure 3-8. Status Register (SR)
Table 3-3. SR Field Descriptions
NOTE
Condition Code Register (CCR)
8
7
6
5
0
0
0
1
0
0
0
Description
Access: Supervisor read/write
BDM read/write
8
7
6
5
4
3
2
1
0
Access: Supervisor read/write
BDM read/write
4
3
2
1
X
N
Z
V
—
—
—
—
Freescale Semiconductor
0
C
—
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